Datasheet SN74CBT16212ADGGR, SN74CBT16212ADGVR, SN74CBT16212ADL, SN74CBT16212ADLR, SNJ54CBT16212AWD Datasheet (Texas Instruments)

FUNCTION

SN54CBT16212A, SN74CBT16212A

24-BIT FET BUS-EXCHANGE SWITCHES

SCDS007M – NOVEMBER 1992 – REVISED SEPTEMBER 1998

D

5-Ω Switch Connection Between Two Ports

D

TTL-Compatible Input Levels

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

ESD Protection Exceeds 2000 V Per
MIL-STD-833, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and Shrink
Small-Outline (DL) Packages, and Ceramic
Flat (WD) Package

description

The ’CBT16212A devices provide 24 bits of
high-speed TTL-compatible bus switching or
exchanging. The low on-state resistance of the
switch allows connections to be made with
minimal propagation delay.

Each device operates as a 24-bit bus switch or a
12-bit bus exchanger, which provides data
exchanging between the four signal ports via the
data-select (S0, S1, S2) terminals.

The SN54CBT16212A is characterized for
operation over the full military temperature range
of –55°C to 125°C. The SN74CBT16212A is
characterized for operation from –40°C to 85°C.

SN54CBT16212A ...WD PACKAGE

SN74CBT16212A . . . DGG, DGV, OR DL PACKAGE

S0
1A1
1A2
2A1
2A2
3A1
3A2

GND

4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2

V

CC

8A1

GND

8A2
9A1
9A2

10A1
10A2

1 1A1

1 1A2
12A1
12A2

(TOP VIEW)

1

56

2

55

3

54

4

53

5

52

6

51

7

50

8

49

9

48

10

47

11

46

12

45

13

44

14

43

15

42

16

41

17

40

18

39

19

38

20

37

21

36

22

35

23

34

24

33

25

32

26

31

27

30

28

29

S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
1 1B1
1 1B2
12B1
12B2

INPUTS

S2 S1 S0 A1 A2

L L L Z Z Disconnect
L L H B1 port Z A1 port = B1 port
L H L B2 port Z A1 port = B2 port

L HH Z B1 port A2 port = B1 port
H LL ZB2 port A2 port = B2 port
H LH Z Z Disconnect

H H L B1 port B2 port

H H H B2 port B1 port

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

FUNCTION TABLE

INPUTS/OUTPUTS

A1 port = B1 port
A2 port = B2 port

A1 port = B2 port
A2 port = B1 port

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.

1

SN54CBT16212A, SN74CBT16212A
24-BIT FET BUS-EXCHANGE SWITCHES

SCDS007M – NOVEMBER 1992 – REVISED SEPTEMBER 1998

logic diagram (positive logic)

1A1

1A2

12A1

12A2

2

3

27

28

54

53

30

29

1B1

1B2

12B1

12B2

1

S0

56

S1

55

S2

Pin numbers shown are for the DGG, DGV, and DL packages.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

UNIT

PARAMETER

TEST CONDITIONS

UNIT

I

A
¶

on

V

0

SN54CBT16212A, SN74CBT16212A

24-BIT FET BUS-EXCHANGE SWITCHES

SCDS007M – NOVEMBER 1992 – REVISED SEPTEMBER 1998

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

†

Continuous channel current 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I
Package thermal impedance, θ

(V

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

JA

DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 3)

SN54CBT16212A SN74CBT16212A

MIN MAX MIN MAX

V
V
V
T

NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 4 5.5 4 5.5 V

CC

High-level control input voltage 2 2 V

IH

Low-level control input voltage 0.8 0.8 V

IL

Operating free-air temperature –55 125 –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

SN54CBT16212A SN74CBT16212A

MIN TYP‡MAX MIN TYP‡MAX

V

IK

I

I

CC

Control

§

∆I

CC

inputs

i
io(OFF)

Control
inputs

C
C

r

‡

All typical values are at VCC = 5 V (unless otherwise noted), TA = 25°C.

§

This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.

¶

Measured by the voltage drop between the A and B terminals at the indicated current through the switch. On-state resistance is determined by
the lower of the voltages of the two (A or B) terminals.

VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 0, VI = 5.5 V 10 10
VCC = 5.5 V, VI = 5.5 V or GND ±1 ±1
VCC = 5.5 V,

VI = VCC or GND
VCC = 5.5 V,

Other inputs at VCC or GND
VI = 3 V or 0 2.5 2.5 pF
VO = 3 V or 0, S0, S1, or S2 = V

VCC = 4 V,
TYP at VCC = 4 V

VCC = 4.5 V

IO = 0,

One input at 3.4 V ,

CC

VI = 2.4 V, II = 15 mA 14 20 14 20

=

I

VI = 2.4 V, II = 15 mA 6 14 6 12

II = 64 mA 4 10 4 7
II = 30 mA 4 10 4 7

3.2 3 µA

2.5 2.5 mA

7.5 7.5 pF

µ

Ω

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN54CBT16212A, SN74CBT16212A
24-BIT FET BUS-EXCHANGE SWITCHES

SCDS007M – NOVEMBER 1992 – REVISED SEPTEMBER 1998

switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)

SN54CBT16212A SN74CBT16212A

PARAMETER

†

t

pd

t

pd

t

en

t

dis

* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†

The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load capacitance, when
driven by an ideal voltage source (zero output impedance).

FROM

(INPUT)

A or B B or A 0.8* 0.35 0.25 ns

S A or B 14 1.5 13 10 1.5 9.1 ns
S A or B 15 1.5 13.7 10.4 1.5 9.7 ns
S A or B 14.2 1.5 13.5 9.2 1.5 8.8 ns

PARAMETER MEASUREMENT INFORMATION

TO

(OUTPUT)

VCC = 4 V

MIN MAX MIN MAX MIN MAX MIN MAX

VCC = 5 V

± 0.5 V

VCC = 4 V

VCC = 5 V

± 0.5 V

UNIT

From Output

Under Test

CL = 50 pF

(see Note A)

LOAD CIRCUIT

Input

t

PLH

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.

E. t
F. t

G. t

1.5 V 1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

and t

PLZ
PZL
PLH

and t
and t

PHZ
PZH

PHL

500 Ω

500 Ω

1.5 V 1.5 V

are the same as t
are the same as ten.
are the same as tpd.

dis

.

S1

t

PHL

7 V

Open

GND

3 V

0 V

V

OH

V

OL

Output

Control
(low-level
enabling)

Output

Waveform 1

S1 at 7 V

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

TEST S1

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

t

PZL

1.5 V

t

PZH

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

t

PLZ

t

PHZ

1.5 V

Open

7 V

Open

1.5 V1.5 V

VOL + 0.3 V

VOH – 0.3 V

3 V

0 V

3.5 V

V

OL

V

OH

0 V

Figure 1. Load Circuit and Voltage Waveforms

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Copyright  1998, Texas Instruments Incorporated