TEXAS INSTRUMENTS SN74CB3T16212 Technical data

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S0
1A1
1A2
2A1
2A2
3A1
3A2

GND

4A1
4A2
5A1
5A2
6A1
6A2
7A1
7A2
V

CC

8A1

GND

8A2
9A1
9A2

10A1
10A2
11A1
11A2
12A1
12A2

S1
S2
1B1
1B2
2B1
2B2
3B1
GND
3B2
4B1
4B2
5B1
5B2
6B1
6B2
7B1
7B2
8B1
GND
8B2
9B1
9B2
10B1
10B2
11B1
11B2
12B1
12B2

DGG OR DGV PACKAGE

(TOP VIEW)

查询74CB3T16212DGGRE4供应商

FEATURES

• Member of the Texas Instruments Widebus™

Family

• Output Voltage Translation Tracks V

• Supports Mixed-Mode Signal Operation on All

Data I/O Ports
– 5-V Input Down to 3.3-V Output Level Shift

With 3.3-V V

– 5-V/3.3-V Input Down to 2.5-V Output Level

Shift With 2.5-V V

• 5-V-Tolerant I/Os With Device Powered Up or

Powered Down

• Bidirectional Data Flow, With Near-Zero

Propagation Delay

• Low ON-State Resistance (r

(r

on

• Low Input/Output Capacitance Minimizes

Loading (C

• Data and Control Inputs Provide Undershoot

Clamp Diodes

• Low Power Consumption (I

• V

CC

• Data I/Os Support 0-V to 5-V Signaling Levels

(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)

• Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

• I

off

Operation

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model(A114-B, Class II)
– 1000-V Charged-Device Model (C101)

• Supports Digital Applications: Level

Translation, PCI Interface, USB Interface,
Memory Interleaving, and Bus Isolation

• Ideal for Low-Power Portable Equipment

DESCRIPTION/ORDERING INFORMATION

The SN74CB3T16212 is a high-speed TTL-compatible FET bus-exchange switch, with low ON-state resistance
(r

), allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data

on

I/O ports by providing voltage translation that tracks V

3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1).

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH

WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005

CC

CC

CC

) Characteristics

= 5 Ω Typ)

= 9 pF Typ)

io(OFF)

Operating Range From 2.3 V to 3.6 V

Supports Partial-Power-Down Mode

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

on

= 70 µ A Max)

CC

. The SN74CB3T16212 supports systems using 5-V TTL,

CC

Copyright © 2003–2005, Texas Instruments Incorporated

SN74CB3T16212

www.ti.com

V

CC

V

CC

5.5 V

0 V

Input Voltages Output Voltages

0 V

VCC − 1 V VCC − 1 V

V

CC

IN OUT

CB3T

NOTE: If the input high-voltage (VIH) level is greater than or equal to VCC − 1 V and less than or equal to 5.5 V , the

output high-voltage (VOH) level is equal to approximately the VCC voltage level.

SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005

Figure 1. Typical DC Voltage Translation Characteristics

The SN74CB3T16212 operates as a 24-bit bus switch or as a 12-bit bus exchange that provides data
exchanging between four signal ports. The select (S0, S1, S2) inputs control the data path of the bus-exchange
switch. When the bus-exchange switch is ON, the A port is connected to the B port, allowing bidirectional data
flow between ports. When the bus-exchange switch is OFF, a high-impedance state exists between the A and B
ports.

This device is fully specified for partial-power-down applications using I
current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, each select input should be tied to GND
through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of
the driver.

off

. The I

feature ensures that damaging

off

ORDERING INFORMATION

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

T

A

TSSOP – DGG Tape and reel SN74CB3T16212DGGR CB3T16212

–40 ° C to 85 ° C

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

TVSOP – DGV Tape and reel SN74CB3T16212DGVR KR212
VFBGA – GQL Tape and reel SN74CB3T16212GQLR
VFBGA – ZQL (Pb-free) Tape and reel SN74CB3T16212ZQLR

PACKAGE

KR212

2

www.ti.com

GQL OR ZQL PACKAGE

(TOP VIEW)

A
B
C
D

E

F
G
H

J

K

1 2 3 4 5 6

24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH

WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005

TERMINAL ASSIGNMENTS

1 2 3 4 5 6

A 1A2 1A1 S0 S1 S2 1B1
B 3A1 2A2 2A1 1B2 2B1 2B2
C 4A1 GND 3A2 3B1 GND 3B2
D 5A2 4A2 5A1 4B2 4B1 5B1
E 6A2 6A1 5B2 6B1
F 7A1 7A2 7B1 6B2
G V
H 8A2 9A1 9A2 9B2 9B1 8B2

J 10A1 10A2 11A1 11B1 10B2 10B1

K 11A2 12A1 12A2 12B2 12B1 11B2

CC

GND 8A1 8B1 GND 7B2

SN74CB3T16212

FUNCTION TABLE

INPUTS INPUTS/OUTPUTS

S2 S1 S0 A1 A2

L L L Z Z Disconnect
L L H B1 port Z A1 port = B1 port
L H L B2 port Z A1 port = B2 port
L H H Z B1 port A2 port = B1 port
H L L Z B2 port A2 port = B2 port
H L H Z Z Disconnect

H H L B1 port B2 port

H H H B2 port B1 port

FUNCTION

A1 port = B1 port
A2 port = B2 port

A1 port = B2 port
A2 port = B1 port

3

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12B2

12B1

1B2

1B1

12A2

12A1

1A2

1A1

S0

S1

S2

SW

SW

SW

SW

SW

SW

SW

SW

2

3

27

28

54

53

30

29

1

56

55

SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005

LOGIC DIAGRAM (POSITIVE LOGIC)

4

www.ti.com

A

EN

(see Note B)

B

Control

Circuit

VG (see Note A)

24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH

WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005

SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)

SN74CB3T16212

A. Gate voltage (V

) is equal to approximately V

G

+ VTwhen the switch is ON and VI> V

CC

+ VT.

CC

B. EN is the internal enable signal applied to the switch.

ABSOLUTE MAXIMUM RATINGS

(1)

over free-air temperature range (unless otherwise noted)

MIN MAX UNIT

V

CC

V

IN

V

I/O

I

IK

I

I/OK

I

I/O

Supply voltage range
Control input voltage range
Switch I/O voltage range
Control input clamp current VIN< 0 –50 mA
I/O port clamp current V
ON-state switch current
Continuous current through V

θ

JA

T

stg

Package thermal impedance

Storage temperature range –65 150 ° C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output volrage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VIand VOare used to denote specific conditions for V
(5) IIand IOare used to denote specific conditions for I
(6) The package thermal impedance is calculated in accordance with JESD 51-7.

(2)

(2) (3)

(2) (3) (4)

< 0 –50 mA

(5)

or GND ± 100 mA

CC

I/O

–0.5 7 V
–0.5 7 V
–0.5 7 V

DGG package 64

(6)

DGV package 48 ° C/W
GQL/ZQL package 42

.

I/O

.

I/O

± 128 mA

RECOMMENDED OPERATING CONDITIONS

V

CC

V

IH

V

IL

V

I/O

T

A

(1) All unused control inputs of the device must be held at V

Supply voltage 2.3 3.6 V

High-level control input voltage V

Low-level control input voltage V

Data input/output voltage 0 5.5 V
Operating free-air temperature –40 85 ° C

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(1)

MIN MAX UNIT

V

= 2.3 V to 2.7 V 1.7 5.5

CC

V

= 2.7 V to 3.6 V 2 5.5

CC

V

= 2.3 V to 2.7 V 0 0.7

CC

V

= 2.7 V to 3.6 V 0 0.8

CC

or GND to ensure proper device operation. Refer to the TI application report,

CC

5

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SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005

ELECTRICAL CHARACTERISTICS

PARAMETER TEST CONDITIONS MIN TYP

V

IK

V

OH

Control

I

IN

inputs

I

I

(3)

I

OZ

I

off

I

CC

Control

(4)

∆ I

CC

inputs
Control

C

in

inputs

C

io(OFF)

C

io(ON)

(5)

r

ON

(1) VINand IINrefer to control inputs. VI, VO, II, and IOrefer to data pins.
(2) All typical values are at V
(3) For I/O ports, the parameter IOZincludes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
(5) Measured by the voltage drop between A and B terminals at the indicated current throught the switch. ON-state resistance is determined

by the lower of the voltages of the two (A or B) terminals.

V

= 3 V, II= –18 mA –1.2 V

CC

See Figures 3 and 4
V

= 3.6 V, VIN= 3.6 V to 5.5 V or GND ± 10 µ A

CC

V

= 3.6 V, VIN= V

CC

V

= 3.6 V, VI= 0, VIN= V

CC

V

= 0, VI= 0, VO= 0 to 5.5 V 10 µ A

CC

V

= 3.6 V, VIN= V

CC

Switch ON or OFF

V

= 3 V to 3.6 V, One input at V

CC

V

= 3.3 V, VIN= V

CC

V

= 3.3 V, VIN= V

CC

V

= 3.3 V, VIN= V

CC

V

= 2.3 V, TYP at V

CC

V

= 3 V, VI= 0

CC

= 3.3 V (unless otherwise noted), TA= 25 ° C.

CC

(1)

(2)

VI= V

or GND, Switch ON VI= 0.7 V to V

CC

– 0.7 V to 5.5 V ± 20

CC

– 0.7 V –40 µ A

CC

VI= 0 to 0.7 V ± 5

or GND, VO= 0 to 5.5 V, Switch OFF ± 10 µ A

CC

CC

or GND, I

= 0,

I/O

VI= V

or GND 70

CC

VI= 5.5 V 70

– 0.6 V, Other inputs at V

CC

or GND 4 pF

CC

or GND, V

CC

or GND, Switch ON pF

CC

= 2.5 V, VI= 0

CC

= 5.5 V, 3.3 V, or GND, Switch OFF 9 pF

I/O

V

= 5.5 V or 3.3 V 8

I/O

V

= GND 23

I/O

IO= 24 mA 5 9.5
IO= 16 mA 5 9.5

or GND 300 µ A

CC

IO= 64 mA 5 8.5
IO= 32 mA 5 8.5

or GND.

CC

MAX UNIT

µ A

Ω

SWITCHING CHARACTERISTICS

over operating free-air temperature range (unless otherwise noted) (see Figure 2 )

V

= 2.5 V V

PARAMETER UNIT

(1)

t

pd

t

pd(s)

t

en

t

dis

FROM TO

(INPUT) (OUTPUT)

A or B B or A 0.15 0.25 ns

S A 1 15.5 1 11.5 ns
S B 1 15 1 12 ns
S B 1 12 1 10.5 ns

CC

± 0.2 V ± 0.3 V

MIN MAX MIN MAX

(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load

capaitance, when driven by an ideal voltage source (zero output impedance).

6

= 3.3 V

CC

www.ti.com

V

OH

V

OL

C

L

(see Note A)

TEST CIRCUIT

S1

2 × V

CC

Open

GND

R

L

R

L

t

PLH

t

PHL

Output

Waveform 1

S1 at 2 × V

CC

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

t

PZL

t

PZH

t

PLZ

t

PHZ

V

CC

0 V

V

OH

V

OL

0 V

VOL + V

∆

VOH − V

∆

0 V

Output

Control

(VIN)

V

CC

V

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (t

pd(s)

)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as t

pd(s)

. The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance

of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.

50 Ω

V

G1

V

CC

DUT

50 Ω

V

IN

50 Ω

V

G2

50 Ω

V

I

TEST

R

L

S1 V

∆

C

L

2.5 V ± 0.2 V

3.3 V ± 0.3 V

V

CC

V

I

t

PHZ/tPZH

t

PLZ/tPZL

t

pd(s)

2.5 V ± 0.2 V

3.3 V ± 0.3 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

Open
Open

2 × V

CC

2 × V

CC

Open
Open

500 Ω
500 Ω

500 Ω
500 Ω

500 Ω
500 Ω

3.6 V or GND

5.5 V or GND
GND

GND

3.6 V

5.5 V

30 pF
50 pF

30 pF
50 pF

30 pF
50 pF

0.15 V

0.3 V

0.15 V

0.3 V

Output

Control

(VIN)

Input Generator

Input Generator

VCC/2 VCC/2

VCC/2 VCC/2

VCC/2 VCC/2

VCC/2

VCC/2

V

O

24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH

WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005

PARAMETER MEASUREMENT INFORMATION

SN74CB3T16212

Figure 2. Test Circuit and Voltage Waveforms

7

www.ti.com

V − Output Voltage − V

OUTPUT VOLTAGE vs INPUT VOLTAGE

O

V

I

− Input Voltage − V

V − Output Voltage − V

OUTPUT VOLTAGE vs INPUT VOLTAGE

O

V

I

− Input Voltage − V

0.0

1.0

2.0

3.0

4.0

0.0 1.0 2.0 3.0 4.0 5.0 6.0

0.0

1.0

2.0

3.0

4.0

0.0

1.0

2.0

3.0

4.0

5.0

6.0

V

CC

= 3 V

I

O

= 1 µA

T

A

= 25°C

V

CC

= 2.3 V

I

O

= 1 µA

T

A

= 25°C

1.5

2.0

2.5

3.0

3.5

4.0

2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

1.5

2.0

2.5

3.0

3.5

4.0

2.3 2.5 2.7 2.9 3.1

3.3

3.5 3.7

1.5

2.0

2.5

3.0

3.5

4.0

2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

V − Output Voltage High − V

OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE

OH

V

CC

− Supply Voltage − V

V

CC

= 2.3 V ~ 3.6 V

VI = 5.5 V
T

A

= 85°C

OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE

V

CC

− Supply Voltage − V

V

CC

= 2.3 V ~ 3.6 V

VI = 5.5 V
T

A

= 25°C

V − Output Voltage High − V

OH

100 µA
8 mA

16 mA
24 mA

100 µA
8 mA

16 mA
24 mA

100 µA
8 mA

16 mA
24 mA

OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE

V

CC

− Supply Voltage − V

V

CC

= 2.3 V ~ 3.6 V

VI = 5.5 V
TA = -40°C

V − Output Voltage High − V

OH

SN74CB3T16212
24-BIT FET BUS-EXCHANGE SWITCH, 2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH
WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS157A – OCTOBER 2003 – REVISED FEBRUARY 2005

TYPICAL CHARACTERISTICS

Figure 3. Data Output Voltage vs Data Input Voltage

Figure 4. V

8

Values

OH

PACKAGE OPTION ADDENDUM

www.ti.com

2-Jun-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package
Drawing

Pins Package

Qty

Eco Plan

74CB3T16212DGGRE4 ACTIVE TSSOP DGG 56 2000 Pb-Free

74CB3T16212DGVRE4 ACTIVE TVSOP DGV 56 2000 Pb-Free

SN74CB3T16212DGGR ACTIVE TSSOP DGG 56 2000 Pb-Free

SN74CB3T16212DGVR ACTIVE TVSOP DGV 56 2000 Pb-Free

SN74CB3T16212ZQLR ACTIVE VFBGA ZQL 56 1000 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

SNAGCU Level-1-260C-UNLIM

(3)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,40

24

112

A

0,23
0,13

13

0,07

4,50
4,30

M

6,60
6,20

0,16 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

1,20 MAX

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

0,15
0,05

14

3,70

3,50

Seating Plane

3,50

20

5,10

4,90

0,08

5,103,70

4,90

382416

7,90

7,70

48

9,80

9,60

56

11,40

11,20

4073251/E 08/00

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50

48

1

1,20 MAX

0,27
0,17

25

24

A

0,15
0,05

0,08

M

6,20

8,30

6,00

7,90

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

DIM

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

PINS **

A MAX

A MIN

48

12,60

12,40

56

14,10

13,90

64

17,10

16,90

4040078/F 12/97

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