TEXAS INSTRUMENTS SN74CB3T16210 Technical data

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DGG OR DGV PACKAGE

(TOP VIEW)

NC - No internal connection

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

NC
1A1
1A2
1A3
1A4
1A5
1A6

GND

1A7
1A8
1A9

1A10

2A1
2A2
V

CC

2A3

GND

2A4
2A5
2A6
2A7
2A8
2A9

2A10

1OE
2OE
1B1
1B2
1B3
1B4
1B5
GND
1B6
1B7
1B8
1B9
1B10
2B1
2B2
2B3
GND
2B4
2B5
2B6
2B7
2B8
2B9
2B10

查询74CB3T16210DGGRE4供应商

FEATURES

• Member of the Texas Instruments Widebus™

Family

• Output Voltage Translation Tracks V

• Supports Mixed-Mode Signal Operation on All

Data I/O Ports
– 5-V Input Down to 3.3-V Output Level Shift

With 3.3-V V

– 5-V/3.3-V Input Down to 2.5-V Output Level

Shift With 2.5-V V

• 5-V-Tolerant I/Os With Device Powered Up or

Powered Down

• Bidirectional Data Flow With Near-Zero

Propagation Delay

• Low ON-State Resistance (r

(r

on

• Low Input/Output Capacitance Minimizes

Loading (C

• Data and Control Inputs Provide Undershoot

Clamp Diodes

• Low Power Consumption

(I

CC

• V

CC

• Data I/Os Support 0- to 5-V Signaling Levels

(0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)

• Control Inputs Can Be Driven by TTL or

5-V/3.3-V CMOS Outputs

• I

off

Operation

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Performance Tested Per JESD 22

– 2000-V Human-Body Model

(A114-B, Class II)

– 1000-V Charged-Device Model (C101)

• Supports Digital Applications: Level

Translation, PCI Interface, USB Interface,
Memory Interleaving, and Bus Isolation

• Ideal for Low-Power Portable Equipment

DESCRIPTION/ORDERING INFORMATION

The SN74CB3T16210 is a high-speed TTL-compatible FET bus switch with low ON-state resistance (r
allowing for minimal propagation delay. The device fully supports mixed-mode signal operation on all data I/O
ports by providing voltage translation that tracks V

3.3-V LVTTL, and 2.5-V CMOS switching standards, as well as user-defined switching levels (see Figure 1 ).

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

20-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

CC

CC

CC

) Characteristics

= 5 Ω Typ)

= 5 pF Typ)

io(OFF)

= 40 µ A Max)

Operating Range From 2.3 V to 3.6 V

Supports Partial-Power-Down Mode

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

on

. The SN74CB3T16210 supports systems using 5-V TTL,

CC

Copyright © 2003–2005, Texas Instruments Incorporated

SN74CB3T16210

),

on

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V

CC

V

CC

5.5 V

0 V

If the input high voltage (VIH) level is greater than or equal to VCC - 1 V , and less than or equal to 5.5 V, the output high voltage (VOH) level will
be equal to approximately the VCC voltage level.

Input Voltages Output Voltages

0 V

VCC - 1 V VCC - 1 V

V

CC

IN OUT

CB3T

SN74CB3T16210
20-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

The SN74CB3T16210 is organized as two 10-bit bus switches with separate ouput-enable (1 OE, 2 OE) inputs. It
can be used as two 10-bit bus switches or as one 20-bit bus switch. When OE is low, the associated 10-bit bus
switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE
is high, the associated 10-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using I
current will not backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

T

A

–40 ° C to 85 ° C

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

TSSOP – DGG Tape and reel SN74CB3T16210DGGR CB3T16210
TVSOP – DGV Tape and reel SN74CB3T16210DGVR KR210

PACKAGE

(1)

ORDERABLE PART NUMBER TOP-SIDE MARKING

FUNCTION TABLE

(EACH 10-BIT BUS SWITCH)

INPUT INPUT/OUTPUT

OE A

L B A port = B port

H Z Disconnect

. The I

off

FUNCTION

feature ensures that damaging

off

through a pullup

CC

Figure 1. Typical DC Voltage Translation Characteristics

2

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GQL PACKAGE

(TOP VIEW)

J

H

G

F

E

D

C

B

A

21 3 4 65

K

1A1

SW

1B1

1A10

1OE

SW

1B10

2A1

SW

2B1

2A10

2OE

SW

2B10

2

12

48

13

24

47

46

36

35

25

20-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

TERMINAL ASSIGNMENTS

1 2 3 4 5 6

A 1A2 1A1 NC 1 OE 2 OE 1B1
B 1A5 1A4 1A3 1B2 1B3 1B4
C NC GND 1A6 1B5 1B6 NC
D 1A8 NC 1A7 NC 1B7 1B8
E 1A10 1A9 1B9 1B10
F 2A1 2A2 2B2 2B1
G V
H NC NC 2A4 2B5 NC NC
J 2A5 2A6 2A7 2B7 2B6 2B5
K 2A8 2A9 2A10 2B10 2B9 2B8

(1) NC - No internal connection

LOGIC DIAGRAM (POSITIVE LOGIC)

GND 2A3 GND 2B4 2B3

CC

SN74CB3T16210

(1)

3

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A

EN

(2)

B

Control

Circuit

V

G

(1)

(1) Gate voltage (VG) is equal to approximately VCC + VT when the switch is ON
and VI > VCC + VT.
(2) EN is the internal enable signal applied to the switch.

SN74CB3T16210
20-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)

Absolute Maximum Ratings

(1)

over operating free-air temperature range (unless otherwise noted)

MIN MAX UNIT

V

CC

V

IN

V

I/O

I

IK

I

I/OK

I

IO

θ

JA

T

stg

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VIand VOare used to denote specific conditions for V
(5) IIand IOare used to denote specific conditions for I
(6) The package thermal impedance is calculated in accordance with JESD 51-7.

Supply voltage range –0.5 7 V

(2) (3) (4)

(2) (3)

–0.5 7 V
–0.5 7 V

Control input voltage range
Switch I/O voltage range
Control input clamp current VIN< 0 –50 mA
I/O port clamp current V
ON-state switch current
Continuous current through V

Package thermal impedance

(5)

or GND ± 100 mA

CC

(6)

< 0 –50 mA

I/O

DGG package 70
DGV package 58

± 128 mA

Storage temperature range –65 150 ° C

.

I/O

.

I/O

° C/W

4

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2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

Recommended Operating Conditions

V

V

V

V
T

A

(1) All unused control inputs of the device must be held at V

Supply voltage 2.3 3.6 V

CC

High-level control input voltage V

IH

Low-level control input voltage V

IL

Data input/output voltage 0 5.5 V

I/O

Operating free-air temperature –40 85 ° C

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(1)

SN74CB3T16210

20-BIT FET BUS SWITCH

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

MIN MAX UNIT

V

= 2.3 V to 2.7 V 1.7 5.5

CC

V

= 2.7 V to 3.6 V 2 5.5

CC

V

= 2.3 V to 2.7 V 0 0.7

CC

V

= 2.7 V to 3.6 V 0 0.8

CC

or GND to ensure proper device operation. Refer to the TI application report,

CC

Electrical Characteristics

PARAMETER TEST CONDITIONS UNIT

V

IK

V

OH

I

IN

I

I

I

OZ

I

off

I

CC

∆ I

CC

C

in

C

io(OFF)

C

io(ON)

(5)

r

on

Control
inputs

(3)

Control

(4)

inputs
Control

inputs

V
See Figure 3 and Figure 4

V

V
Switch ON, VI= 0.7 V to V
VIN= V

V
V

V
Switch ON or OFF, VIN= V

V

V
V

V

V

V

(1)

TA= –40 ° C TO 85 ° C

MIN TYP

= 3 V, II= –18 mA –1.2 V

CC

= 3.6 V, VIN= 3.6 V to 5.5 V or GND ± 10 µ A

CC

= 3.6 V,

CC

or GND

CC

= 3.6 V, VO= 0 to 5.5 V, VI= 0, Switch OFF, VIN= V

CC

= 0, VO= 0 to 5.5 V, VI= 0, 10 µ A

CC

= 3.6 V, I

CC

= 3 V to 3.6 V, One input at V

CC

= 3.3 V, VIN= V

CC

= 3.3 V, V

CC

= 3.3 V, Switch ON, VIN= V

CC

= 2.3 V, TYP at V

CC

= 3 V, VI= 0

CC

= 0,

I/O

CC

= 5.5 V, 3.3 V, or GND, Switch OFF, VIN= V

I/O

or GND

CC

– 0.6 V, Other inputs at V

CC

or GND 4 pF

or GND pF

CC

= 2.5 V, VI= 0

CC

VI= V

VI= 0 to 0.7 V ± 5

VI= V
VI= 5.5 V 40

V
V
IO= 24 mA 5 9.5
IO= 16 mA 5 9.5
IO= 64 mA 5 8.5
IO= 32 mA 5 8.5

– 0.7 V to 5.5 V ± 20

CC

– 0.7 V –40 µ A

CC

or GND ± 10 µ A

CC

or GND 40

CC

or GND 300 µ A

CC

or GND 5 pF

CC

= 5.5 V or 3.3 V 5

I/O

= GND 13

I/O

(1) VINand IINrefer to control inputs. VI, VO, II, and IOrefer to data pins.
(2) All typical values are at V
(3) For I/O ports, the parameter IOZincludes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
(5) Measured by the voltage drop between A and B terminals at the indicated current through the switch. ON-state resistance is determined

= 3.3 V (unless otherwise noted), TA= 25 ° C.

CC

or GND.

CC

by the lower of the voltages of the two (A or B) terminals.

(2)

MAX

µ A

Ω

5

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SN74CB3T16210
20-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

Switching Characteristics

for V

= 2.5 V ± 0.2 V (see Figure 2 )

CC

V

= 2.5 V V

PARAMETER UNIT

(1)

t

pd

t

en

t

dis

(1) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load

capacitance, when driven by an ideal voltage source (zero output impedance).

FROM TO

(INPUT) (OUTPUT)

A or B B or A 0.15 0.25 ns

OE A or B 1 12 1 10 ns
OE A or B 1 7.5 1 8.5 ns

CC

± 0.2 V ± 0.3 V

MIN MAX MIN MAX

CC

= 3.3 V

6

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V

OH

V

OL

C

L

(see Note A)

TEST CIRCUIT

S1

2 × V

CC

Open

GND

R

L

R

L

t

PLH

t

PHL

Output

Waveform 1

S1 at 2 × V

CC

(see Note B)

Output

Waveform 2

S1 at Open

(see Note B)

t

PZL

t

PZH

t

PLZ

t

PHZ

V

CC

0 V

V

OH

V

OL

0 V

VOL + V

∆

VOH - V

∆

0 V

Output

Control

(VIN)

V

CC

V

CC

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES (t

pd(s)

)

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as t

pd(s)

. The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance

of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).

H. All parameters and waveforms are not applicable to all devices.

50 Ω

V

G1

V

CC

DUT

50 Ω

V

IN

50 Ω

V

G2

50 Ω

V

I

TEST

R

L

S1 V

∆

C

L

2.5 V ± 0.2 V

3.3 V ± 0.3 V

V

CC

V

I

t

PHZ/tPZH

t

PLZ/tPZL

t

pd(s)

2.5 V ± 0.2 V

3.3 V ± 0.3 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

Open
Open

2 × V

CC

2 × V

CC

Open
Open

500 Ω
500 Ω

500 Ω
500 Ω

500 Ω
500 Ω

3.6 V or GND

5.5 V or GND
GND

GND

3.6 V

5.5 V

30 pF
50 pF

30 pF
50 pF

30 pF
50 pF

0.15 V

0.3 V

0.15 V

0.3 V

Output

Control

(VIN)

Input Generator

Input Generator

VCC/2 VCC/2

VCC/2 VCC/2

VCC/2 VCC/2

VCC/2

VCC/2

V

O

20-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

SN74CB3T16210

Figure 2. Test Circuit and Voltage Waveforms

7

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OUTPUT VOLTAGE vs INPUT VOLTAGE

V

I

- Input Voltage - V

OUTPUT VOLTAGE vs INPUT VOLTAGE

V

I

- Input Voltage - V

0

1

2

3

4

0 1 2 3 4 5 6

0

1

2

3

4

0 1 2 3 4 5 6

V

CC

= 3 V

I

O

= 1 µA

T

A

= 25°C

V

CC

= 2.3 V

I

O

= 1 µA

T

A

= 25°C

V

O

- Output Voltage - V

V

O

- Output Voltage - V

SN74CB3T16210
20-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

TYPICAL CHARACTERISTICS

Figure 3. Data Output Voltage vs Data Input Voltage

8

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1.5

2

2.5

3

3.5

4

2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

1.5

2

2.5

3

3.5

4

2.3 2.5 2.7 2.9 3.1

3.3

3.5 3.7

1.5

2

2.5

3

3.5

4

2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE

V

CC

- Supply Voltage - V

V

CC

= 2.3 V ~ 3.6 V

VI = 5.5 V
T

A

= 85°C

OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE

V

CC

- Supply Voltage - V

V

CC

= 2.3 V ~ 3.6 V

VI = 5.5 V
T

A

= 25°C

100 µA

8 mA

16 mA

24 mA

100 µA

8 mA

16 mA

24 mA

100 µA

8 mA

16 mA

24 mA

OUTPUT VOLTAGE HIGH vs SUPPLY VOLTAGE

V

CC

- Supply Voltage - V

V

CC

= 2.3 V ~ 3.6 V

VI = 5.5 V
TA = -40°C

V

OH

- Output Voltage High - V

V

OH

- Output Voltage High - V
V

OH

- Output Voltage High - V

20-BIT FET BUS SWITCH

2.5-V/3.3-V LOW-VOLTAGE BUS SWITCH WITH 5-V-TOLERANT LEVEL SHIFTER

SCDS156A – OCTOBER 2003 – REVISED MARCH 2005

TYPICAL CHARACTERISTICS

SN74CB3T16210

Figure 4. V

Values

OH

9

PACKAGE OPTION ADDENDUM

www.ti.com

19-May-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package

Drawing

Pins Package

Qty

Eco Plan

74CB3T16210DGGRE4 ACTIVE TSSOP DGG 48 2000 Pb-Free

74CB3T16210DGVRE4 ACTIVE TVSOP DGV 48 2000 Pb-Free

SN74CB3T16210DGG PREVIEW TSSOP DGG 48 40 Pb-Free

SN74CB3T16210DGGR ACTIVE TSSOP DGG 48 2000 Pb-Free

SN74CB3T16210DGVR ACTIVE TVSOP DGV 48 2000 Pb-Free

SN74CB3T16210DL PREVIEW SSOP DL 48 25 TBD Call TI Call TI

SN74CB3T16210DLR PREVIEW SSOP DL 48 1000 TBD Call TI Call TI

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

(3)

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.

Addendum-Page 1

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**) PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,40

24

112

A

0,23
0,13

13

0,07

4,50
4,30

M

6,60
6,20

0,16 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

1,20 MAX

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

0,15
0,05

14

3,70

3,50

Seating Plane

3,50

20

5,10

4,90

0,08

5,103,70

4,90

382416

7,90

7,70

48

9,80

9,60

56

11,40

11,20

4073251/E 08/00

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

48

1

0.110 (2,79) MAX

0.0135 (0,343)

0.008 (0,203)
25

0.299 (7,59)

0.291 (7,39)

24

A

0.008 (0,20) MIN

0.005 (0,13)

0.420 (10,67)

0.395 (10,03)

Seating Plane

0.004 (0,10)

M

0.010 (0,25)

0.005 (0,13)

Gage Plane

0.010 (0,25)

0°–ā8°

0.040 (1,02)

0.020 (0,51)

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118

0.380

(9,65)

0.370

(9,40)

4828

0.630

(16,00)

0.620

(15,75)

56

0.730

(18,54)

0.720

(18,29)

4040048/E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50

48

1

1,20 MAX

0,27
0,17

25

24

A

0,15
0,05

0,08

M

6,20

8,30

6,00

7,90

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

DIM

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

PINS **

A MAX

A MIN

48

12,60

12,40

56

14,10

13,90

64

17,10

16,90

4040078/F 12/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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