TEXAS INSTRUMENTS SN74CB3Q3305 Technical data
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PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OE
1A
1B
GND
V
CC
2OE
2B
2A
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SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
FEATURES
• High-Bandwidth Data Path (up to 500 MHz
• 5-V Tolerant I/Os With Device Powered Up or
Powered Down • V
• Low and Flat ON-State Resistance (r
(1)
)
) • Data I/Os Support 0- to 5-V Signaling Levels
on
• Data and Control Inputs Provide Undershoot
Clamp Diodes
• Low Power Consumption (I
Operating Range From 2.3 V to 3.6 V
CC
CC
Characteristics Over Operating Range (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
(r
= 3 Ω Typ)
on
• Control Inputs Can Be Driven by TTL or
• Rail-to-Rail Switching on Data I/O Ports 5-V/3.3-V CMOS Outputs
– 0- to 5-V Switching With 3.3-V V
– 0- to 3.3-V Switching With 2.5-V V
• Bidirectional Data Flow With Near-Zero
Propagation Delay
• Low Input/Output Capacitance Minimizes
CC
CC
• I
Supports Partial-Power-Down Mode
off
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
Loading and Signal Distortion – 2000-V Human-Body Model
(C
• Fast Switching Frequency (f
= 3.5 pF Typ) (A114-B, Class II)
io(OFF)
= 20 MHz Max) – 1000-V Charged-Device Model (C101)
OE
• Supports Both Digital and Analog
(1) For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI application
report, CBT-C, CB3T, and CB3Q Signal-Switch Families,
literature number SCDA008. Signal Gating
Applications: USB Interface, Differential
Signal Interface, Bus Isolation, Low-Distortion
= 0.25 mA Typ)
DESCRIPTION/ORDERING INFORMATION
The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (r
for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device
also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
The SN74CB3Q3305 is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can
be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus switch is
ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is low, the
associated 1-bit bus switch is OFF and a high-impedance state exists between the A and B ports.
–40°C to 85°C TSSOP – PW BU305
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
). The low and flat ON-state resistance allows
on
ORDERING INFORMATION
Tube SN74CB3Q3305PW
Tape and reel SN74CB3Q3305PWR
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Copyright © 2003–2005, Texas Instruments Incorporated
T
A
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PACKAGE
www.ti.com
1A
1OE
SW
1B
2A
2OE
SW
2B
2
1
5
7
3
6
A
EN
(1)
B
(1) EN is the internal enable signal applied to the switch.
Charge
Pump
V
CC
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using I
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
FUNCTION TABLE
(EACH BUS SWITCH)
INPUT INPUT/OUTPUT
OE A
H B A port = B port
L Z Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
. The I
off
FUNCTION
circuitry prevents damaging
off
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
2
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SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
V
Supply voltage range –0.5 4.6 V
CC
V
Control input voltage range
IN
V
Switch I/O voltage range
I/O
I
Control input clamp current VIN< 0 –50 mA
IK
I
I/O port clamp current V
I/OK
I
ON-state switch current
I/O
Continuous current through V
θ
Package thermal impedance
JA
T
Storage temperature range –65 150 °C
stg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VIand VOare used to denote specific conditions for V
(5) IIand IOare used to denote specific conditions for I
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
(5)
(1)
(2) (3)
(2) (3) (4)
< 0 –50 mA
I/O
or GND ±100 mA
CC
(6)
.
I/O
.
I/O
MIN MAX UNIT
–0.5 7 V
–0.5 7 V
±64 mA
88 °C/W
Recommended Operating Conditions
V
V
V
V
T
A
Supply voltage 2.3 3.6 V
CC
High-level control input voltage V
IH
Low-level control input voltage V
IL
Data input/output voltage 0 5.5 V
I/O
Operating free-air temperature –40 85 °C
(1)
(1) All unused control inputs of the device must be held at V
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
MIN MAX UNIT
V
= 2.3 V to 2.7 V 1.7 5.5
CC
V
= 2.7 V to 3.6 V 2 5.5
CC
V
= 2.3 V to 2.7 V 0 0.7
CC
V
= 2.7 V to 3.6 V 0 0.8
CC
or GND to ensure proper device operation. Refer to the TI application report,
CC
3
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