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PW PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OE
1A
1B
GND
V
CC
2OE
2B
2A
查询74CB3Q3305DCURE4供应商
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
FEATURES
• High-Bandwidth Data Path (up to 500 MHz
• 5-V Tolerant I/Os With Device Powered Up or
Powered Down • V
• Low and Flat ON-State Resistance (r
(1)
)
) • Data I/Os Support 0- to 5-V Signaling Levels
on
• Data and Control Inputs Provide Undershoot
Clamp Diodes
• Low Power Consumption (I
Operating Range From 2.3 V to 3.6 V
CC
CC
Characteristics Over Operating Range (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
(r
= 3 Ω Typ)
on
• Control Inputs Can Be Driven by TTL or
• Rail-to-Rail Switching on Data I/O Ports 5-V/3.3-V CMOS Outputs
– 0- to 5-V Switching With 3.3-V V
– 0- to 3.3-V Switching With 2.5-V V
• Bidirectional Data Flow With Near-Zero
Propagation Delay
• Low Input/Output Capacitance Minimizes
CC
CC
• I
Supports Partial-Power-Down Mode
off
Operation
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Performance Tested Per JESD 22
Loading and Signal Distortion – 2000-V Human-Body Model
(C
• Fast Switching Frequency (f
= 3.5 pF Typ) (A114-B, Class II)
io(OFF)
= 20 MHz Max) – 1000-V Charged-Device Model (C101)
OE
• Supports Both Digital and Analog
(1) For additional information regarding the performance
characteristics of the CB3Q family, refer to the TI application
report, CBT-C, CB3T, and CB3Q Signal-Switch Families,
literature number SCDA008. Signal Gating
Applications: USB Interface, Differential
Signal Interface, Bus Isolation, Low-Distortion
= 0.25 mA Typ)
DESCRIPTION/ORDERING INFORMATION
The SN74CB3Q3305 is a high-bandwidth FET bus switch utilizing a charge pump to elevate the gate voltage of
the pass transistor, providing a low and flat ON-state resistance (r
for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The device
also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus.
Specifically designed to support high-bandwidth applications, the SN74CB3Q3305 provides an optimized
interface solution ideally suited for broadband communications, networking, and data-intensive computing
systems.
The SN74CB3Q3305 is organized as two 1-bit switches with separate output-enable (1OE, 2OE) inputs. It can
be used as two 1-bit bus switches or as one 2-bit bus switch. When OE is high, the associated 1-bit bus switch is
ON and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is low, the
associated 1-bit bus switch is OFF and a high-impedance state exists between the A and B ports.
–40°C to 85°C TSSOP – PW BU305
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
). The low and flat ON-state resistance allows
on
ORDERING INFORMATION
Tube SN74CB3Q3305PW
Tape and reel SN74CB3Q3305PWR
(1)
ORDERABLE PART NUMBER TOP-SIDE MARKING
Copyright © 2003–2005, Texas Instruments Incorporated
T
A
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PACKAGE
www.ti.com
1A
1OE
SW
1B
2A
2OE
SW
2B
2
1
5
7
3
6
A
EN
(1)
B
(1) EN is the internal enable signal applied to the switch.
Charge
Pump
V
CC
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
This device is fully specified for partial-power-down applications using I
current backflow through the device when it is powered down. The device has isolation during power off.
To ensure the high-impedance state during power up or power down, OE should be tied to GND through a
pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.
FUNCTION TABLE
(EACH BUS SWITCH)
INPUT INPUT/OUTPUT
OE A
H B A port = B port
L Z Disconnect
LOGIC DIAGRAM (POSITIVE LOGIC)
. The I
off
FUNCTION
circuitry prevents damaging
off
SIMPLIFIED SCHEMATIC, EACH FET SWITCH (SW)
2
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SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
V
Supply voltage range –0.5 4.6 V
CC
V
Control input voltage range
IN
V
Switch I/O voltage range
I/O
I
Control input clamp current VIN< 0 –50 mA
IK
I
I/O port clamp current V
I/OK
I
ON-state switch current
I/O
Continuous current through V
θ
Package thermal impedance
JA
T
Storage temperature range –65 150 °C
stg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground, unless otherwise specified.
(3) The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) VIand VOare used to denote specific conditions for V
(5) IIand IOare used to denote specific conditions for I
(6) The package thermal impedance is calculated in accordance with JESD 51-7.
(5)
(1)
(2) (3)
(2) (3) (4)
< 0 –50 mA
I/O
or GND ±100 mA
CC
(6)
.
I/O
.
I/O
MIN MAX UNIT
–0.5 7 V
–0.5 7 V
±64 mA
88 °C/W
Recommended Operating Conditions
V
V
V
V
T
A
Supply voltage 2.3 3.6 V
CC
High-level control input voltage V
IH
Low-level control input voltage V
IL
Data input/output voltage 0 5.5 V
I/O
Operating free-air temperature –40 85 °C
(1)
(1) All unused control inputs of the device must be held at V
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
MIN MAX UNIT
V
= 2.3 V to 2.7 V 1.7 5.5
CC
V
= 2.7 V to 3.6 V 2 5.5
CC
V
= 2.3 V to 2.7 V 0 0.7
CC
V
= 2.7 V to 3.6 V 0 0.8
CC
or GND to ensure proper device operation. Refer to the TI application report,
CC
3
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SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP
V
IK
I
IN
I
OZ
I
off
I
CC
∆ I
CC
I
CCD
C
in
C
io(OFF)
C
io(ON)
(6)
r
on
Control
inputs
(3)
Control
(4)
inputs
Per control mA/
(5)
input MHz
Control
inputs
(1) VINand IINrefer to control inputs. VI, VO, II, and IOrefer to data pins.
(2) All typical values are at V
(3) For I/O ports, the parameter IOZincludes the input leakage current.
(4) This is the increase in supply current for each input that is at the specified TTL voltage level, rather than V
(5) This parameter specifies the dynamic power-supply current associated with the operating frequency of a single control input (see
Figure 2 ).
(6) Measured by the voltage drop between the A and B terminals at the indicated current through the switch. ON-state resistance is
determined by the lower of the voltages of the two (A or B) terminals.
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
Control input switching at 50% duty cycle
V
CC
V
CC
V
CC
V
CC
TYP at V
V
CC
(1)
(2)
MAX UNIT
= 3.6 V, II= –18 mA –1.8 V
= 3.6 V, VIN= 0 to 5.5 V ±1 µ A
= 3.6 V, ±1 µ A
VO= 0 to 5.5 V, Switch OFF,
VI= 0, VIN= V
or GND
CC
= 0, VO= 0 to 5.5 V, VI= 0 1 µ A
I
= 0,
= 3.6 V, VIN= V
= 3.6 V, One input at 3 V, Other inputs at V
= 3.6 V, A and B ports open,
I/O
Switch ON or OFF,
or GND 0.25 0.7 mA
CC
or GND 25 µ A
CC
0.040 0.045
= 3.3 V, VIN= 5.5 V, 3.3 V, or 0 2.5 3.5 pF
= 3.3 V, V
= 3.3 V, V
= 2.3 V,
= 2.5 V
CC
= 3 V
= 3.3 V (unless otherwise noted), TA= 25°C.
CC
Switch OFF,
VIN= V
Switch ON,
VIN= V
or GND,
CC
or GND,
CC
= 5.5 V, 3.3 V, or 0 3.5 5 pF
I/O
= 5.5 V, 3.3 V, or 0 8 10.5 pF
I/O
VI= 0, IO= 30 mA 3 8
VI= 1.7 V, IO= –15 mA 3.5 9
VI= 0, IO= 30 mA 3 6
VI= 2.4 V, IO= –15 mA 3.5 8
or GND.
CC
Ω
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 3 )
V
= 2.5 V V
PARAMETER UNIT
(1)
f
OE
(2)
t
pd
t
en
t
dis
(1) Maximum switching frequency for control input (V
(2) The propagation delay is the calculated RC time constant of the typical ON-state resistance of the switch and the specified load
FROM TO
(INPUT) (OUTPUT)
OE A or B 10 20 MHz
A or B B or A 0.09 0.15 ns
OE A or B 1 5 1 4.5 ns
OE A or B 1 4.5 1 5 ns
> VCC, VI= 5 V, RL≥ 1 M Ω , CL= 0)
O
CC
± 0.2 V ± 0.3 V
MIN MAX MIN MAX
capacitance, when driven by an ideal voltage source (zero output impedance).
4
CC
= 3.3 V
www.ti.com
0
2
4
6
8
10
12
14
16
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
r
on
- ON-State Resistance -
VI - V
TYPICAL r
on
vs
V
I
Ω
V
CC
= 3.3 V
TA = 25°C
IO = -15 mA
0
2
4
6
8
10
12
0 2 4 6 8 10 12 14 16 18 20
OE Switching Frequency − MHz
TYPICAL ICC
vs
OE SWITCHING FREQUENCY
CC
I − mA
VCC = 3.3 V
TA = 25°C
A and B Ports Open
One OE Switching
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
SN74CB3Q3305
Figure 1. Typical r
Figure 2. Typical ICCvs OE Switching Frequency
vs V
on
I
5
www.ti.com
V
OH
V
OL
C
L
(see Note A)
TEST CIRCUIT
S1
2 × V
CC
Open
GND
R
L
R
L
t
PLH
t
PHL
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
V
OH
V
OL
0 V
VOL + V
∆
VOH − V
∆
0 V
Output
Control
(VIN)
V
CC
V
CC
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES (t
pd(s)
)
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time, with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as t
pd(s)
. The tpd propagation delay is the calculated RC time constant of the typical ON-state resistance
of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance).
H. All parameters and waveforms are not applicable to all devices.
50 Ω
V
G1
V
CC
DUT
50 Ω
V
IN
50 Ω
V
G2
50 Ω
V
I
TEST
R
L
S1 V
∆
C
L
2.5 V ± 0.2 V
3.3 V ± 0.3 V
V
CC
V
I
t
PHZ/tPZH
t
PLZ/tPZL
t
pd(s)
2.5 V ± 0.2 V
3.3 V ± 0.3 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
Open
Open
2 × V
CC
2 × V
CC
GND
GND
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
500 Ω
VCC or GND
VCC or GND
GND
GND
V
CC
V
CC
30 pF
50 pF
30 pF
50 pF
30 pF
50 pF
0.15 V
0.3 V
0.15 V
0.3 V
Output
Control
(VIN)
Input Generator
Input Generator
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
V
O
SN74CB3Q3305
DUAL FET BUS SWITCH
2.5-V/3.3-V LOW-VOLTAGE HIGH-BANDWIDTH BUS SWITCH
SCDS141A – OCTOBER 2003 – REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
6
Figure 3. Test Circuit and Voltage Waveforms
PACKAGE OPTION ADDENDUM
www.ti.com
8-Aug-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
74CB3Q3305DCURE4 ACTIVE US8 DCU 8 3000 Pb-Free
SN74CB3Q3305DCUR ACTIVE US8 DCU 8 3000 Pb-Free
SN74CB3Q3305PW ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br)
SN74CB3Q3305PWE4 ACTIVE TSSOP PW 8 150 Green (RoHS &
no Sb/Br)
SN74CB3Q3305PWR ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br)
SN74CB3Q3305PWRE4 ACTIVE TSSOP PW 8 2000 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
(3)
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,65
1,20 MAX
14
0,30
0,19
8
4,50
4,30
PINS **
7
Seating Plane
0,15
0,05
8
1
A
DIM
14
0,10
6,60
6,20
M
0,10
0,15 NOM
0°–8°
2016
Gage Plane
24
0,25
0,75
0,50
28
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
7,70
9,80
9,60
4040064/F 01/97
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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