SN74BCT756
OCTAL BUFFER/DRIVER
WITH OPEN-COLLECTOR OUTPUTS
SCBS056B – OCTOBER 1990 – REVISED JUL Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
BiCMOS Design Significantly Reduces I
CCZ
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Open-Collector Outputs Drive Bus Lines or
Buffer Memory Address Registers
D
Package Options Include Plastic
Small-Outline Packages (DW) and Standard
Plastic 300-mil DIPs (N)
description
This octal buffer and line driver is designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. The SN74BCT756, SN74BCT757,
and SN74BCT760 provide the choice of selected
combinations of inverting outputs, symmetrical
output-enable (OE
) inputs, and complementary
OE and OE inputs.
The SN74BCT756 is characterized for operation
from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
OE A
Y
H X H
L LH
L H L
logic symbol
†
2
1A1
4
1A2
6
1A3
8
1A4
EN
1
1Y1
18
1Y2
16
1Y3
14
1Y4
12
11
2A1
13
2A2
15
2A3
17
2A4
EN
19
2Y1
9
2Y2
7
2Y3
5
2Y4
3
1OE 2OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Copyright 1997, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
DW OR N PACKAGE
(TOP VIEW)
SN74BCT756
OCTAL BUFFER/DRIVER
WITH OPEN-COLLECTOR OUTPUTS
SCBS056B – OCTOBER 1990 – REVISED JUL Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
2
18
1OE
1A1
1Y1
4
16
1A2
1Y2
6
14
1A3
1Y3
8
12
1A4
1Y4
19
11
9
2OE
2A1
2Y1
13
7
2A2
2Y2
15
5
2A3
2Y3
17
3
2A4
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range, I
I
–30 mA to 5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, VO –0.5 V to 5.5 V. . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, VO –0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 1): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
OH
High-level output voltage 5.5 V
I
IK
Input clamp current –18 mA
I
OL
Low-level output current 64 mA
T
A
Operating free-air temperature 0 70 °C
SN74BCT756
OCTAL BUFFER/DRIVER
WITH OPEN-COLLECTOR OUTPUTS
SCBS056B – OCTOBER 1990 – REVISED JUL Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
I
OH
VCC = 4.5 V, VOH = 5.5 V 0.1 mA
V
OL
VCC = 4.5 V, IOL = 64 mA 0.42 0.55 V
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V 20 µA
I
IL
VCC = 5.5 V, VI = 0.5 V –1 mA
Outputs high 21 33
I
CC
VCC = 5.5 V, Outputs open
Outputs low
55 86
mA
OE disable 6 10
C
i
VCC = 5 V, VI = 2.5 V or 0.5 V 6 pF
C
o
VCC = 5 V, VI = 2.5 V or 0.5 V 10 pF
†
All typical values are at VCC = 5 V, TA = 25°C.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Figure 1)
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
VCC = 5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = 25°C
VCC = 4.5 to 5.5 V,
CL = 50 pF,
R1 = 500 Ω,
R2 = 500 Ω,
TA = MIN to MAX
‡
UNIT
MIN TYP MAX MIN MAX
t
PLH
6.2 8.5 10.5 6.2 11.3
t
PHL
A
Y
0.5 2 4.1 0.5 4.2
ns
t
PLH
8.2 12.5 14.8 8.2 16.5
t
PHL
OE
Y
3.4 6.8 9.2 3.4 10.3
ns
‡
For conditions as MIN or MAX, use the appropriate value specified under recommended operating conditions.
SN74BCT756
OCTAL BUFFER/DRIVER
WITH OPEN-COLLECTOR OUTPUTS
SCBS056B – OCTOBER 1990 – REVISED JUL Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
3 V
0 V
Input
Out-of-Phase
Output
In-Phase
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Output
Control
(low-level
enable)
High-Level
Pulse
Output
Waveform 2
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
3.5 V
0 V
0 V
3 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr =tf ≤ 2.5 ns, duty cycle = 50%.
D. The outputs are measured one at a time with one input transition per measurement.
0.3 V
0.3 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
0 V
0 V
t
h
t
su
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Data Input
Timing Input
3 V
3 V
1.5 V
1.5 V 1.5 V
C
L
(see Note A)
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
3 V
0 V
1.5 V 1.5 V
3 V
0 V
1.5 V 1.5 V
Low-Level
Pulse
t
w
From Output
Under Test
7 V
(t
PZL
, t
PLZ
, O.C.)
Open
(all others)
Test
Point
R2
RL = R1 = R2
S1
R1
Output
Waveform 1
(see Note B)
Figure 1. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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Copyright 1998, Texas Instruments Incorporated
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