DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
LE
SN74BCT29843
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS022C – FEBRUARY 1989 – REVISED NOVEMBER 1993
Copyright 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• BiCMOS Process With CMOS Inputs and
TTL Outputs Substantially Reduces
Standby Current
• Input Has 50 kΩ
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN74BCT29843 features 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. It is particularly
suitable for implementing wider buffer registers,
I/O ports, bidirectional bus drivers with parity , and
working registers.
The nine latches are transparent D-type latches. When the latch-enable (LE) input is high, the Q outputs are
complementary to the noninverting data (D) inputs.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low level) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus
lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines without
need for interface or pull-up components.
The output enable (OE
) does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74BCT29843 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT
PRE CLR OE LE D
Q
L X L X X H
H LLXX L
H HLHL L
H HLHH H
H HLLX Q
0
X X H X X Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74BCT29843
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS022C – FEBRUARY 1989 – REVISED NOVEMBER 1993
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
logic diagram (positive logic)
1Q
23
2Q
22
3Q
21
4Q
20
5Q
19
OE
1D
2
1D
3
2D
4
3D
5
4D
6
5D
S2
14
6Q
18
7Q
17
8Q
16
9Q
15
7
6D
8
7D
9
8D
10
9D
EN
1
OE
LE
1D
1Q
1
13
2
23
To Eight Other Channels
C1
13
LE
R
11
PRE
CLR
PRE
14
CLR
11
S
C1
1D
R
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, V
O
–0.5 V to 7 V. . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
–0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only, and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –24 mA
I
OL
Low-level output current 48 mA
T
A
Operating free-air temperature 0 70 °C
SN74BCT29843
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS022C – FEBRUARY 1989 – REVISED NOVEMBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
IOH = –15 mA 2.4 3.2
V
OH
V
CC
=
4.5 V
IOH = –24 mA 2
V
V
OL
VCC = 4.5 V, IOL = 48 mA 0.35 0.55 V
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V –10 –75 µA
I
IL
VCC = 5.5 V, VI = 0.4 V –0.2 mA
I
OS
‡
VCC = 5.5 V, VO = 0 –75 –275 mA
I
CCL
VCC = 5.5 V, Outputs open 24 35 mA
I
CCH
VCC = 5.5 V, Outputs open 3 7 mA
I
CCZ
VCC = 5.5 V, Outputs open 3 7 mA
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
MIN MAX UNIT
PRE low 7
t
w
Pulse duration
CLR
low 5
ns
LE high 4
p
High or low 1.5
tsuSetup time, data before LE↓
PRE or CLR inactive 2
ns
t
h
Hold time, data after LE↓ High or low 3.5 ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Note 2)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
MIN MAX UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX
t
PLH
1.5 4.5 7 1.5 8
t
PHL
D
Q
1.5 5.7 8 1.5 9
ns
t
PLH
1.5 6 8 1.5 10
t
PHL
LE
Q
1.5 6 8 1.5 10
ns
t
PLH
1.5 6 8 1.5 12
t
PHL
PRE
Q
1.5 6 10 1.5 12
ns
t
PLH
1.5 6 10 1.5 12
t
PHL
CLR
Q
1.5 6 10 1.5 12
ns
t
PZH
2 10 13 2 15
t
PZL
OE
Q
2 10 13 2 15
ns
t
PHZ
2 5 7 2 8
t
PLZ
OE
Q
2 5 7 2 8
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
SN74BCT29843
9-BIT BUS-INTERFACE D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCBS022C – FEBRUARY 1989 – REVISED NOVEMBER 1993
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated
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