Texas Instruments SN74BCT29834DW, SN74BCT29834DWR, SN74BCT29834NT Datasheet
DW OR NT PACKAGE
(TOP VIEW)
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24
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15
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13
OEA
A1
A2
A3
A4
A5
A6
A7
A8
ERR
CLR
GND
V
CC
B1
B2
B3
B4
B5
B6
B7
B8
PARITY
OEB
CLK
SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
Copyright 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• BiCMOS Process With TTL Inputs and
Outputs
• BiCMOS Design Reduces Standby Current
• Flow-Through Pinout (All Inputs on
Opposite Side From Outputs)
• Functionally Equivalent to SN74ALS29834
and AMD Am29834
• High-Speed Bus Transceiver With Parity
Generator/Checker
• Parity-Error Flag With Open-Collector
Output
• Available Register For Storage of the
Parity-Error Flag
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
The SN74BCT29834 is an 8-bit to 9-bit parity transceiver designed for asynchronous communication between
data buses. When data is transmitted from the A to B bus, a parity bit is generated. When data is transmitted
from the B to A bus with its corresponding parity bit, the parity-error (ERR) output will indicate whether or not
an error in the B data has occurred. The output-enable (OEA
, OEB) inputs can be used to disable the device
so that the buses are effectively isolated.
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with an open-collector parity-error flag (ERR). ERR is clocked into the register on the rising edge of the CLK
input. The error flag register is cleared with a low pulse on the clear (CLR) input. When both OEA and OEB are
low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced
error condition which gives the designer more system diagnostic capability. The SN74BCT29834 provides
inverting logic.
The SN74BCT29834 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
OUTPUT AND I/O
OEB OEA CLR
CLK
Ai
∑ of H’s
Bi
†
∑ of L’s
A B PARITY ERR
‡
FUNCTION
L H X X
Odd
Even
NA NA A
H
L
NA A data to B bus and generate parity
H L H ↑ NA
Odd
Even
B NA NA
H
L
B data to A bus and check parity
X X L X X X X NA NA H Clear error-flag register
H H
H
L
H
H
No↑
No↑
↑
↑
X
X
Odd
Even
X Z Z Z
NC
H
L
H
Isolation
§
L L X X
Odd
Even
NA NA A
L
H
NA
A data to B bus and generate inverted
parity
NA = not applicable, NC = no change, X = don’t care
†
Summation of high-level inputs includes PARITY along with Bi inputs.
‡
Output states shown assume the ERR
output was previously high.
§
In this mode, the ERR
output, when enabled, shows inverted parity of the A bus.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional logic diagram (positive logic)
8x
EN
A1–A8
OEA
OEB
CLK
CLR
G1
1
1
1
1
MUX
2k
EN
8x
B1–B8
PARITY
ERR
88
8
8
8
9
P
R
C1
1D
SN74BCT29834
8-BIT TO 9-BIT PARITY BUS TRANSCEIVER
SCBS256 – SEPTEMBER 1987 – REVISED NOVEMBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
error-flag waveforms
ERR
CLR
CLK
Bi + PARITY
OEA
OEB
Even
H
Odd
L
H
L
H
L
H
L
H
L
t
su
t
PLH
t
w
t
w
t
h
t
su
t
PHL
ERROR-FLAG FUNCTION TABLE
INPUTS
INTERNAL
TO DEVICE
OUTPUT
PRESTATE
OUTPUT
FUNCTION
CLR CLK
POINT P
ERR
n–1
†
ERR
FUNCTION
H
H
H
↑
↑
↑
H
X
L
H
L
X
H
L
L
Sample
L X X X H Clear
†
ERR
n–1
represents the state of the ERR output before any changes at CLR, CLK,
or point P.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
‡
Supply voltage, V
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, V
I
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to a disabled I/O port 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
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