DW OR NT PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
CLKEN
CLK
SN74BCT29823
9-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCBS018D – NOVEMBER 1988 – REVISED NOVEMBER 1993
Copyright 1993, Texas Instruments Incorporated
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
• State-of-the-Art BiCMOS Design
Significantly Reduces I
CCZ
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
• 3-State Buffer-Type Outputs Drive Bus
Lines Directly
• Package Options Include Plastic
Small-Outline (DW) Packages and Standard
Plastic 300-mil DIPs (NT)
description
This 9-bit bus-interface flip-flop features 3-state
outputs designed specifically for driving highly
capacitive or relatively low-impedance loads. It is
particularly suitable for implementing wider buffer
registers, I/O ports, bidirectional bus drivers with
parity, and working registers.
The nine flip-flops are edge-triggered D-type flip-flops. With the clock-enable (CLKEN
) input low, the flip-flops
store data on the low-to-high transitions of the clock. T aking CLKEN high disables the clock buf fer, thus latching
the outputs. The SN74BCT29823 has noninverting data (D) inputs. T aking the clear (CLR) input low causes the
nine Q outputs to go low independent of the clock.
A buffered output-enable (OE) input can be used to place the nine outputs in either a normal logic state (high
or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly . The high-impedance state and increased drive provide the capability to drive bus lines without need
for interface or pullup components.
The output enable (OE) does not affect the internal operation of the flip-flops. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The SN74BCT29823 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
OE CLR CLKEN CLK D
OUTPUT
Q
L L X X X L
L HL↑ HH
L HL↑ LL
L HHXX Q
0
H X X X X Z
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
SN74BCT29823
9-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCBS018D – NOVEMBER 1988 – REVISED NOVEMBER 1993
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
EN
1
7
6D
8
7D
9
8D
10
9D
2D
2
1D
6Q
18
7Q
17
8Q
16
9Q
15
1Q
23
3
2D
4
3D
5
4D
6
5D
2Q
22
3Q
21
4Q
20
5Q
19
OE
13
CLK 1C2
R
11
CLR
G1
14
CLKEN
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
To Eight Other Channels
23
2
1
1D
1Q
R
C1
1D
CLKEN
CLK
11
14
13
OE
CLR
SN74BCT29823
9-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCBS018D – NOVEMBER 1988 – REVISED NOVEMBER 1993
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the disabled or power-off state, V
O
–0.5 V to 5.5 V. . . . . . . . . . . . . . . .
Voltage range applied to any output in the high state, V
O
–0.5 V to V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current into any output in the low state, I
O
96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
recommended operating conditions
MIN NOM MAX UNIT
V
CC
Supply voltage 4.5 5 5.5 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
I
IK
Input clamp current –18 mA
I
OH
High-level output current –24 mA
I
OL
Low-level output current 48 mA
T
A
Operating free-air temperature 0 70 °C
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP‡MAX UNIT
V
IK
VCC = 4.5 V, II = –18 mA –1.2 V
IOH = –15 mA 2.4 3.2
V
OH
V
CC
= 4.5
V
IOH = –24 mA 2
V
V
OL
VCC = 4.5 V, IOL = 48 mA 0.35 0.5 V
I
I
VCC = 5.5 V, VI = 7 V 0.1 mA
I
IH
VCC = 5.5 V, VI = 2.7 V –10 –75 µA
I
IL
VCC = 5.5 V, VI = 0.5 V –0.2 mA
I
OS
§
VCC = 5.5 V, VO = 0 –75 –250 mA
I
OZH
VCC = 5.5 V, VO = 2.7 V 20 µA
I
OZL
VCC = 5.5 V, VO = 0.5 V –20 µA
I
CCL
VCC = 5.5 V, Outputs open 25 35 mA
I
CCH
VCC = 5.5 V, Outputs open 6 10 mA
I
CCZ
VCC = 5.5 V, Outputs open 2 6 mA
C
i
VCC = 5 V, VI = 2.5 V or 0.5 V 5.5 pF
C
o
VCC = 5 V, VO = 2.5 V or 0.5 V 7 pF
‡
All typical values are at VCC = 5 V, TA = 25°C.
§
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
SN74BCT29823
9-BIT BUS-INTERFACE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCBS018D – NOVEMBER 1988 – REVISED NOVEMBER 1993
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
VCC = 5 V,
TA = 25°C
MIN MAX UNIT
MIN MAX
f
clock
Clock frequency 0 125 0 125 MHz
CLR low 6 6
twPulse duration
CLK high or low 7 7
ns
CLR inactive 2 2
Data high or low 7 7
t
su
Set
up time before
CLK↑
CLKEN high 6 6
ns
CLKEN low 8 8
Data high or low 1 1
t
h
Hold time after CLK↑
CLKEN high or low 0 0
ns
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 50 pF (unless otherwise noted) (see Note 2)
PARAMETER
FROM
TO
VCC = 5 V,
TA = 25°C
MIN MAX UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX
f
max
125 125 MHz
t
PLH
1.5 7.5 10 1.5 12
t
PHL
CLK
Q
1.5 6.5 9 1.5 10
ns
t
PHL
CLR Q 1.5 7.5 10 1.5 12 ns
t
PZH
2 7.5 10 2 12
t
PZL
OE
Q
2 9 12 2 13
ns
t
PHZ
2 5 7 2 8
t
PLZ
OE
Q
2 5 7 2 8
ns
NOTE 2: Load circuits and voltage waveforms are shown in Section 1.
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
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In order to minimize risks associated with the customer’s applications, adequate design and operating
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Copyright 1998, Texas Instruments Incorporated
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