16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
D
Multiplexed Real-Time and Latched Data
D
Byte Control for Byte-Write Applications
D
Useful in NuBust Interface Applications
D
Useful in Memory Interleave Applications
SN74BCT2423A, SN74BCT2424A
SDIS013 – JULY 1989 – REVISED AUGUST 1990
D
BiCMOS Design Substantially Reduces
Standby Current
D
Dependable Texas Instruments Quality and
Reliability
AENL
ABLEA
ABENL
GND
AB
AB
AB
AB
GND
AB
AB
AB
AB
V
CC
A/BSEL
BLE
BENL
SN74BCT2423A . . . FN PACKAGE
A0
A1
A2
A3
A4
8765493
10
11
12
13
7
14
6
15
5
16
4
17
18
3
19
2
20
1
21
0
22
23
24
25
26
27
28 29
31 32 33 34
30
A5
A6
(TOP VIEW)
A7
GND
A8
168672
35 36 37 38 39
A9
66 65
A10
A1 1
64 63 62 61
40 41 42 43
A12
A13
A14
A15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
AENM
ALE
V
CC
V
CC
AB15
AB
14
13
AB
AB
12
GND
11
AB
AB
10
9
AB
AB
8
GND
ABENM
ABLEB
BENM
B2B3B4
B0
B1
NuBus is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
B5B6B7
B8
GND
B9
B10
B1 1
B12
B13
B14
B15
Copyright 1990, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
AENL
ABLEA
ABENL
GND
AB7
AB6
AB5
AB4
GND
AB3
AB2
AB1
AB0
V
CC
A/BSEL
BLE
BENL
SN74BCT2424A . . . FN PACKAGE
A0
A1
A2
A3
8765493
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
28 29
27
30
31 32 33 34
A4
(TOP VIEW)
A5
A6
A7
35 36 37 38 39
GND
168672
A8
A9
A10
66 65
A1 1
A12
A13
64 63 62 61
40 41 42 43
A14
A15
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
AENM
ALE
V
CC
V
CC
AB15
AB14
AB13
AB12
GND
AB1 1
AB10
AB9
AB8
GND
ABENM
ABLEB
BENM
B8
B0
B1
B3B4B5
B2
B6
B7
GND
B9
B10
B1 1
B12
B13
B14
B15
description
The ’BCT2423A and ’BCT2424A are general-purpose 16-bit bidirectional transceivers with data storage latches
and byte control circuitry arranged for use in applications where two separate data paths must be multiplexed
onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing
of address and data information in microprocessor- or bus-interface applications. These devices are also useful
in memory-interleaving applications. The ’BCT2423A and ’BCT2424A offer inverted and noninverted data
paths, respectively.
The ’BCT2423A and ’BCT2424A were designed using Texas Instruments BiCMOS process, which features
bipolar drive characteristics, but also greatly reduces the standby power of the device when disabled. This is
valuable when the device is not performing an address or data transfer.
Three 16-bit I/O ports, A15–A0, B15–B0, and AB15–AB0 are available for address and/or data transfer. The
AENM
, AENL, BENM, BENL, ABENM, and ABENL inputs control the bus transceiver functions. These control
signals also allow byte-control of the most significant byte and least significant byte for each bus.
Address and/or data information can be stored using the internal storage latches. The ALE
ABLEB
inputs are active low, and are used to control data storage. When the latch enable input is low , the latch
is transparent. When the latch enable input goes high, the data present at the inputs is latched, and remains
latched until the latch enable input is returned low.
Data on the ’A ’ bus and ’B’ bus are multiplexed onto the ’AB’ bus via the A
is low, A15–A0 is mapped to the AB15 –AB0 outputs. When A
/BSEL is high, B15 –B0 is mapped to the
/BSEL control line. When A/BSEL
AB15–AB0 outputs.
, BLE, ABLEA, and
The SN74BCT2423A and SN74BCT2424A are characterized for operation from 0°C to 70°C.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic symbol for the ’BCT2423A
59
10
60
9
2
66
61
24
27
34
36
AENL
AENM
A
/BSEL
ALE
A0
A7
A8
A15
B0
B7
B8
†
ALE
AENL
AENM
0
7
8
15
ASEL
BSEL
0
7
8
LATCHED MUX/DMUX
’BCT2423A
AL
AM
BL
Φ
11
45
12
46
22
19
17
14
48
51
53
ABLEA
ABLEB
ABENL
ABENM
0
AB
AB
3
AB
4
AB7
AB
8
AB
11
AB
12
ABL
ABM
ABLEA
ABLEB
ABENL
ABENM
0
3
4
7
8
11
12
BM
B15
BLE
BENL
BENM
†
These logic symbols are in accordance with ANSI/IEEE Std 91-1984.
43
25
26
44
15
BLE
BENL
BENM
13
56
AB
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic symbol for the ’BCT2424A
59
10
60
9
2
66
61
24
27
AENL
AENM
A
/BSEL
ALE
A0
A7
A8
A15
B0
†
ALE
AENL
AENM
0
7
8
15
ASEL
BSEL
0
LATCHED MUX/DMUX
’BCT2424A
AL
AM
Φ
11
45
12
46
22
19
17
14
48
ABLEA
ABLEB
ABENL
ABENM
AB0
AB3
AB4
AB7
AB8
ABL
ABLEA
ABLEB
ABENL
ABENM
0
3
4
7
8
BL
B7
B8
B15
BLE
BENL
BENM
†
These logic symbols are in accordance with ANSI/IEEE Std 91-1984.
34
36
43
25
26
44
7
8
BM
15
BLE
BENL
BENM
ABM
11
12
13
51
53
56
AB11
AB12
AB15
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
logic diagram for ’BCT2423A (positive logic)
AENL
A7–A0
8
8
C1
SN74BCT2423A, SN74BCT2424A
SDIS013 – JULY 1989 – REVISED AUGUST 1990
ABLEA
A15–A8
AENM
ALE
A
/BSEL
BLE
16
16X
16X
8
16
8
16
C1
D1
C1
16 16
D1
G1
1
1
16X
MUX
D1
ABENL
7–AB0
AB
8
16
8
AB
15–AB8
ABENM
BENL
B7–B0
B15–B8
BENM
8
8
8
16
8
C1
16X
D1
ABLEB
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
logic diagram for ’BCT2424A (positive logic)
AENL
C1
A7–A0
8
8
ABLEA
A15–A8
AENM
ALE
A
/BSEL
BLE
16
8
16
C1
D1
C1
16 16
D1
16X
16X
8
16
G1
1
16X
D1
ABENL
MUX
8
16
8
1
AB7–AB0
AB15–AB8
ABENM
BENL
B7–B0
B15–B8
BENM
8
8
8
16
8
C1
16X
D1
ABLEB
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
Terminal Functions
TERMINAL PINS DESCRIPTION
A bus. This 16-bit I/O port allows for transmission of data and/or address information to or from the AB bus.
A15–A0
AB 15–AB0
(’BCT 2423A)
AB 15–AB0
(’BCT 2424A)
ABENL
ABENM
ABLEA
ABLEB
A/BSEL
AENL A Bus Output Enable, Least Significant Byte. This active-low input is used to enable the A7–A0 outputs. When this
AENM A Bus Output Enable, Most Significant Byte. This active-low input is used to enable the A15–A8 outputs. When this
ALE A Bus Latch Enable. This active-low input is used to control the latch that holds data received from the A bus
B15–B0 B Bus. This 16-bit I/O port allows for transmission of data and/or address information to or from the AB bus.
BENL B Bus Output Enable, Least Significant Byte. This active-low input is used to enable the B7–B0 outputs. When this
BENM B Bus Output Enable, Most Significant Byte. This active-low input is used to enable the B15–B8 outputs. When this
BLE B Bus Latch Enable. This active-low input is used to control the latch that holds data received from the B bus
Information transfer between the A bus and the AB bus is inverting for the ’BCT2423A and noninverting for the
’BCT2424A.
AB Bus. This 16-bit i/o port allows for multiplexed transmission of data and/or address information to or from the A
and B buses. Information transfer between the A, B, and AB buses is inverting for the ’BCT2423A and noninverting
for the ’BCT2424A.
AB Bus Output Enable, Least Significant Byte. This active-low input is used to enable the AB7–AB0 outputs. When
this input is high, the AB7–AB0 outputs are in the high-impedance state allowing for data input.
AB Bus Latch Enable, Most Significant Byte. This active-low input is used to enable the AB15–AB8 outputs. When
this input is high, the AB15–AB8 outputs are in the high-impedance state allowing for data input.
AB Bus Latch Enable to A Bus. This active-low input is used to control the latch that holds data received from the
AB bus (AB15–AB0) to be transferred to the A bus (A15–A0). When ABLEA
ABLEA
transitions to the high level, the data present at the AB15 –AB0 inputs is latched, and it remains latched while
ABLEA
is high.
AB Bus Latch Enable to B Bus. This active-low input is used to control the latch that holds data received from the
AB bus (AB15–AB0) to be transferred to the B bus (B15–B0). When ABLEB
ABLEB
transitions to the high level, the data present at the AB15 –AB0 inputs is latched, and it remains latched while
ABLEB
is high.
A/B Select Control. This input controls the A/B multiplexer. When the input is low , the A15–A0 is selected as input
to the AB15–AB0 outputs. When the input is high, B15–B0 is selected as input to the AB15–AB0 outputs.
input is high, the A7–A0 outputs are in the high-impedance state allowing for data input.
input is high, the A15–A8 outputs are in the high-impedance state allowing for data input.
(A15 –A0). When ALE
the A15–A0 inputs is latched and remains latched while ALE
Information transfer between the B bus and the AB bus is inverting for the ’BCT2423A and noninverting for the
’BCT2424A.
input is high, the B7–B0 outputs are in the high-impedance state allowing for data input.
input is high, the B15–B8 outputs are in the high-impedance state allowing for data input.
(B15–B0). When BLE
the B15–B0 inputs is latched and remains latched while BLE
is low, that latch is transparent. When ALE transitions to the high level, the data present at
is low, that latch is transparent. When BLE transitions to the high level, that data present at
SN74BCT2423A, SN74BCT2424A
SDIS013 – JULY 1989 – REVISED AUGUST 1990
is low, the latch is transparent. When
is low, the latch is transparent. When
is high.
is high.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74BCT2423A, SN74BCT2424A
INPUTS
ABLEA
ABLEB
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
Function Tables
DIRECTION A OR B TO AB
OUTPUTS
’BCT2423A ’BCT2424A
Ax Bx ALE BLE A/BSEL ABENM ABENL AB 15–8 AB 7–0 AB 15–8 AB 7–0
H X L X L L L L H
L XLX L LL H L
XXHX L LL AB
X H X L H L L L H
X LXLHLL H L
XXXHH LL AB
X X X X X L L Active Active Active Active
X X X X X L H Active Z Active Z
X XXX X HL ZActive Z Active
X X X X X H H Z Z Z Z
DIRECTION AB TO A OR B
INPUTS OUTPUTS
ABx
ABx
H L L L L L L H H
L LLLLH HLL
HLHLL L B
LLHLL H B
HHLLLA
LHLLLA
XHHLLA
XXXLLActive Active Active Active
X X X L H Active Z Active Z
X XXHL ZActive Z Active
X X X H H Z Z Z Z
H = high level, L = low level, X = irrelevant, Z = high impedance.
A0, B0, AB0, AB
†
The least significant bytes (A7-A0 and B7-B0) and the most significant bytes (A15-A8 and B15-B8) can be independently enabled and
disabled, as was illustrated for the AB
= no change since the controlling latch enable went high
0
and AB bytes in the upper function table.
AENL
AENM
†
†
BENL
BENM
†
†
’BCT2423A ’BCT2424A
Ax Bx Ax Bx
0
0
0
0
0
0
0
LA
HA
B
0
H B
L B
0
0
A
0
AB
0
AB
0
H
L
B
0
0
0
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IOHHigh-level output current
mA
IOLLow-level output current
mA
twPulse duration
ns
V
A
B
ts
V
A
B
outputs
I
mA
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
absolute maximum ratings over operating free-air temperature range(unless otherwise noted)
Supply voltage, V
Input voltage (all inputs and I/O ports) 5.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65° to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions beyond those indicated in the “recommended operating conditions” section of
this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
(see Note 1) 7V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
recommended operating conditions
PARAMETER MIN NOM MAX UNIT
V
CC
V
IH
V
IL
t
su
t
h
T
A
Supply voltage 4.75 5 5.25 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
p
p
Setup time Data before xLEx ↑ 10 ns
Hold time Data after xLEx ↑ 2 ns
Operating free-air temperature 0 70 °C
Ax, Bx outputs –15
ABx or ABx outputs –15
Ax, Bx outputs 24
ABx or ABx outputs 48
ABLEA, ABLEB high or low 12.5
ALE, BLE high or low 12.5
†
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP
V
IK
V
OH
p
,
outpu
X
x
OL
p
,
X
x
I
I
‡
I
IH
‡
I
IL
§
I
OS
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
For I/O ports, the parameter IIH and IIL include the offstate output current.
§
Not more than one output should be shorted at a time, and duration of the short circuit should not exceed one second.
Enabled VCC = 5.25V , VIL = 0.5 V, 110 170
Disabled
VCC = 4.75V , II = –18 mA –1.2 V
VCC = 4.75V , IOH = –400 mA VCC – 1.5
VCC = 4.75V , IOH = –3 mA 2.8 3.6
VCC = 4.75V , IOH = –15 mA 2
VCC = 4.75V , IOL = 12 mA 0.25 0.4
VCC = 4.75V , IOL = 24 mA 0.35 0.5
VCC = 4.75V , IOL = 24 mA 0.25 0.4
VCC = 4.75V , IOL = 48 mA 0.35 0.5
VCC = 5.25V , VI = 5.5 V 100
VCC = 5.25V , VI = 2.7 V
VCC = 5.25V , VI = 0.4 V –200
VCC = 5.25V , V0 = 0 –60 –225 mA
VIH = 3V , Outputs open 20 40
†
MAX UNIT
V
m
A
20
m
–100
A
m
A
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN74BCT2423A, SN74BCT2424A
V
CC
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
t
pd
t
pd
t
pd
t
pd
t
pd
t
pd
t
pd
t
pd
t
pd
t
en
t
en
t
en
t
dis
t
dis
t
dis
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
See Parameter Measurement Information for load circuit and voltage waveforms.
FROM
(INPUT)
ABx, ABx Ax 8 12 ns
ABx, ABx Bx 8 12 ns
Ax ABx, ABx 9 12 ns
Bx ABx, ABx 9 12 ns
ALE ↓ ABx, ABx 10 13 ns
BLE ↓ ABx, ABx 10 13 ns
ABLEA ↓ Ax 8 12 ns
ABLEB ↓ Bx 8 12 ns
A/BSEL ABx, ABx
AENM,
AENL
BENM,
BENL
ABENM,
ABENL
AENM,
AENL
BENM,
BENL
ABENM,
ABENL
TO
(OUTPUT)
Ax
Bx
ABx, ABx 10 13 ns
Ax 5 10 ns
Bx 5 10 ns
ABx, ABx 5 10 ns
TEST CONDITIONS
=
= 4.75 V to 5.25 V,
CL = 50 pF,
R1 = 500 Ω, R2 = 500 Ω,
TA = MIN to MAX
‡
MIN TYP†MAX UNIT
10 13 ns
10 13 ns
8 12 ns
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
PARAMETER MEASUREMENT INFORMATION
Timing
Input
Data
Input
SWITCH POSITION TABLE
TEST S1
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
t
su
1.3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Open
Open
Open
Closed
Open
Closed
1.3 V
t
h
1.3 V
3.5 V
0.3 V
3.5 V
0.3 V
From Output
Under Test
(see Note A)
High-Level
Pulse
Low-Level
Input
7 V
RL = R1 = R
S1
R1
C
L
LOAD CIRCUIT
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
R2
2
Test
Point
3.5 V
0.3 V
3.5 V
0.3 V
Input
t
PLH
In-Phase
Output
t
PHL
Out-of-Phase
Output
NOTES: A. CL includes probe and jig capacitance.
B. Wafeform 1 is for an output with internal conditions such that the output is low except when disabled by the current control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
D. The outputs are measured one at a time with one transition per measurement.
1.3 V 1.3 V
1.3 V
1.3 V 1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
PHL
1.3 V
t
PLH
3.5 V
0.3 V
V
OH
V
OL
V
OH
V
OL
Output Control
(Low-level
Enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
ENABLE AND DISABLED TIMES, 3-STATE OUTPUTS
Figure 1
1.3 V 1.3 V
t
PZL
t
PZH
VOLTAGE WAVEFORMS
t
PLZ
1.3 V
t
PHZ
1.3 V
0.3 V
0.3 V
3.5 V
0.3 V
≈ 3.5 V
V
OL
V
OH
≈ 0 V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
11
SN74BCT2423A, SN74BCT2424A
16-BIT LATCHED MULTIPLEXER/DEMULTIPLEXER BUS TRANSCEIVERS
SDIS013 – JULY 1989 – REVISED AUGUST 1990
APPLICATION INFORMATION
’ACT4503
AS
(see Note A)
R/W
M/IO
A3–A22 ADDR BUS
A2 (BANK SELECT
READY
A1 (BYTE
SELECT)
A 2 (BYTE
SELECT)
A3–A12
A13–A22
ALE
ACR
ACW
CS
RA0–RA9
CA0–CA9
RENO
RDY
MA0–MA9
RAS
0
CAS
0
RAS
1
’BCT2424
A0–A9
RAS0
CAS
CAS
W
D
BANK0
1M X 16BIT
DRAMs
Lower
0
1
Upper
Byte
Strobe
Q
D0–D15
DATA BUS
AENM
AENL
ALE
ABLEA
ABENM
AB0–AB15
ABENL
ABLEB
ABSEL
BLE
BENM
A0–A15
B0–B15
BANK1
1M X 16BIT
1
0
1
DRAMs
Lower
Upper
Q
Byte
Strobe
A0–A9
RAS
CAS
CAS
D
W
BENL
NOTE A: The value of this delay element is dependent on the speed of the microprocessor.
Figure 2. Typical Memory Interleave Application
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