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SN74AVCH245
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TEXAS INSTRUMENTS SN74AVCH245 Technical data

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SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
D
DOC
(Dynamic Output Control) Circuit
Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V V
D
Dynamic Drive Capability Is Equivalent to
CC
Standard Outputs With IOH and IOL of ±24 mA at 2.5-V V
CC
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,
Logic Family T echnology and Applications Circuitry Technology and Applications
, literature number SCEA006, and
, literature number SCEA009.
D
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
D
I
Supports Partial-Power-Down Mode
off
Operation
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
Package Options Include Plastic Small-Outline (DW), Thin Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages
Dynamic Output Control (DOC)
AVC
3.2
2.8
2.4
2.0
1.6
1.2
– Output Voltage – V
OL
0.8
V
0.4
TA = 25°C Process = Nominal
VCC = 1.8 V
IOL – Output Current – mA
VCC = 2.5 V
VCC = 3.3 V
136
17015311910285685134170
2.8
2.4
2.0
1.6
1.2
– Output Voltage – V
OH
0.8
V
0.4
TA = 25°C Process = Nominal
VCC = 3.3 V
–128–144–160
IOH – Output Current – mA
VCC = 2.5 V
VCC = 1.8 V
–80–96–112 –32–48–64 0–16
Figure 1. Output Voltage vs Output Current
This octal bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.
The SN74A VCH245 is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are effectively isolated.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE
) input can be used to disable the device so that the buses are effectively isolated.
PRODUCT PREVIEW
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCT PREVIEW information concerns products in the formative or design phase of development. Characteristic data and other specifications are design goals. Texas Instruments reserves the right to change or discontinue these products without notice.
Copyright 2000, Texas Instruments Incorporated
1
SN74AVCH245
OPERATION
OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
description (continued)
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. This device is fully specified for partial-power-down applications using I
preventing damaging current backflow through the device when it is powered down. The SN74AVCH245 is characterized for operation from –40°C to 85°C.
terminal assignments
PRODUCT PREVIEW
DGV, DW, OR PW PACKAGE
OE DIR
H X Isolation
(TOP VIEW)
1
20 19 18 17 16 15 14 13 12 11
V OE B1 B2 B3 B4 B5 B6 B7 B8
CC
DIR
2
A1
3
A2
4
A3
5
A4
6
A5
7
A6
8
A7
9
A8
GND
INPUTS
L L B data to A bus L H A data to B bus
10
FUNCTION TABLE (each transceiver)
off
. The I
circuitry disables the outputs,
off
2
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
DIR
A1
A2 A3 A4 A5 A6 A7 A8
19 1
2
3 4 5 6 7 8 9
G3 3 EN1 [BA]
3 EN2 [AB]
1
2
logic diagram (positive logic)
1
DIR
18
17 16 15 14 13 12 11
B1
B2 B3 B4 B5 B6 B7 B8
A1
19
OE
2
18
B1
PRODUCT PREVIEW
To Seven Other Channels
3
SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2) –0.5 V to V
Voltage range applied to any input/output when the output
is in the high-impedance or power-off state, V
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . .
O
Voltage range applied to any input/output when the output
is in the high or low state, V
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 3): DGV package 92°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 83°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
†
PRODUCT PREVIEW
4
VCCSuppl
oltage
V
VOOutput voltage
V
I
Static high-level output current
†
mA
I
Static low-level output current
†
mA
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
V
V
V
OHS
OLS
∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V T
†
Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and V characteristics. Refer to the TI application reports,
Dynamic Output Control (DOC) Circuitry Technology and Applications
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 3.6 V
I
p
p
p
Operating free-air temperature –40 85 °C
A
AVC Logic Family Technology and Applications
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.4 3.6 Data retention only 1.2 VCC = 1.2 V V VCC = 1.4 V to 1.6 V 0.65 × V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V 2 VCC = 1.2 V GND VCC = 1.4 V to 1.6 V 0.35 × V VCC = 1.65 V to 1.95 V VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8
Active state 0 V 3-state 0 3.6 VCC = 1.4 V to 1.6 V –2 VCC = 1.65 V to 1.95 V –4 VCC = 2.3 V to 2.7 V –8 VCC = 3 V to 3.6 V –12 VCC = 1.4 V to 1.6 V 2 VCC = 1.65 V to 1.95 V 4 VCC = 2.3 V to 2.7 V 8 VCC = 3 V to 3.6 V 12
, literature number SCEA009.
CC
CC
0.65 × V
CC
0.35 × V
CC
, literature number SCEA006, and
CC CC
OH
V
V
vs I
OH
PRODUCT PREVIEW
5
SN74AVCH245
‡
BHL
§
#
CiControl inputs
V
V
GND
pF
C
i
A or B orts
V
O
V
CC
GND
F
OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
I
= –100 µA 1.4 V to 3.6 V VCC–0.2
OHS
I
= –2 mA, VIH = 0.91 V 1.4 V 1.05
OHS
V
OH
V
OL
I
I
I
I
I
I I I
PRODUCT PREVIEW
†
Typical values are measured at TA = 25°C.
‡
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. I then raising it to VIL max.
§
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. I then lowering it to VIH min.
An external driver must source at least I
#
An external driver must sink at least I
||
For I/O ports, the parameter IOZ includes the input leakage current.
Control inputs VI = VCC or GND 3.6 V ±2.5 µA
I
BHL
BHH
BHLO
BHHO
off
||
OZ CC
p
o
p
I
= –4 mA, VIH = 1.07 V 1.65 V 1.2
OHS
I
= –8 mA, VIH = 1.7 V 2.3 V 1.75
OHS
I
= –12 mA, VIH = 2 V 3 V 2.3
OHS
I
= 100 µA 1.4 V to 3.6 V 0.2
OLS
I
= 2 mA, VIL = 0.49 V 1.4 V 0.4
OLS
I
= 4 mA, VIL = 0.57 V 1.65 V 0.45
OLS
I
= 8 mA, VIL = 0.7 V 2.3 V 0.55
OLS
I
= 12 mA, VIL = 0.8 V 3 V 0.7
OLS
VI = 0.57 V 1.65 V 25 VI = 0.7 V 2.3 V 45 VI = 0.8 V 3 V 75 VI = 1.07 V 1.65 V –25 VI = 1.7 V 2.3 V –45 VI = 2 V 3 V –75
VI = 0 to V
VI = 0 to V
VI or VO = 3.6 V 0 ±10 µA VO = VCC or GND 3.6 V ±12.5 µA VI = VCC or GND, IO = 0 3.6 V 40 µA
I
CC
CC
=
or
CC
=
or
to switch this node from low to high.
BHLO
to switch this node from high to low.
BHHO
V
CC
1.95 V 200
2.7 V 300
3.6 V 500
1.95 V –200
2.7 V –300
3.6 V –500
2.5 V
3.3 V
2.5 V
3.3 V
should be measured after lowering VIN to GND and
BHL
should be measured after raising VIN to VCC and
BHH
MIN TYP†MAX UNIT
V
V
µA
µA
µA
µA
p
p
6
(INPUT)
(OUTPUT)
PARAMETER
TEST CONDITIONS
UNIT
C
C
pF
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
PARAMETER
t
pd
t
en
t
dis
FROM
A or B B or A ns
OE OE
TO
A or B ns A or B ns
VCC = 1.2 V
TYP MIN MAX MIN MAX MIN MAX MIN MAX
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
operating characteristics, T
Power dissipation
pd
capacitance
= 25°C
A
Outputs enabled Outputs disabled
= 0,f = 10 MHz
L
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
p
PRODUCT PREVIEW
7
SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 15 pF
(see Note A)
2 kΩ
2 kΩ
V
= 1.2 V AND 1.5 V ± 0.1 V
CC
2 × V
S1
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
PRODUCT PREVIEW
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten.
are the same as tpd.
h
VCC/2 VCC/2
VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.1 V
t
PHZ
VOH – 0.1 V
Figure 2. Load Circuit and Voltage Waveforms
8
From Output
Under Test
CL = 30 pF
(see Note A)
OCTAL BUS TRANSCEIVER
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1 kΩ
1 kΩ
S1
SN74AVCH245
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control (low-level enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
PRODUCT PREVIEW
Figure 3. Load Circuit and Voltage Waveforms
9
SN74AVCH245 OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
PRODUCT PREVIEW
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten.
are the same as tpd.
h
VCC/2 VCC/2
VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
10
Figure 4. Load Circuit and Voltage Waveforms
From Output
Under Test
(see Note A)
CL = 30 pF
SCES264D – APRIL 1999 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 3.3 V ± 0.3 V
V
CC
2 × V
500 Ω
500 Ω
S1
CC
Open
GND
TEST S1
t
t
PLZ/tPZL
t
PHZ/tPZH
SN74AVCH245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
pd
Open
2 × V
GND
CC
Timing
Input
Input
Input
Output
Data
t
PLH
LOAD CIRCUIT
VCC/2
t
su
VCC/2 VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
w
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2 VCC/2
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
PRODUCT PREVIEW
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
F. t
G. t
PLZ PZL PLH
and t and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 5. Load Circuit and Voltage Waveforms
11
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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