Texas Instruments SN74AVC32373GKER Datasheet

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74A VC32373

1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCES327 – APRIL 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

DOC

 (Dynamic Output Control) Circuit

Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation

D

Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V V

CC

D

Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications

D

I

off

Supports Partial-Power-Down Mode

Operation

D

ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Packaged in Plastic Fine-Pitch Ball Grid
Array Package

description

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical VOL vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,

AVC

Logic Family T echnology and Applications

, literature number SCEA006, and

Dynamic Output Control (DOC)

Circuitry Technology and Applications

, literature number SCEA009.

136

–128–144–160

0.4

0.8

1.2

1.6

2.0

2.4

2.8

17015311910285685134170

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2
TA = 25°C

Process = Nominal

IOL – Output Current – mA

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

– Output Voltage – V

OL

V

TA = 25°C
Process = Nominal

IOH – Output Current – mA

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

– Output Voltage – V

OH

V

–80–96–112 –32–48–64 0–16

Figure 1. Output Voltage vs Output Current

This 32-bit transparent D-type latch with is operational from 1.2-V or 3.6-V V

CC

, but is designed specifically for

1.65-V to 3.6-V V

CC

operation.

The SN74AVC32373 can be used as four 8-bit latches, two 16-bit latches, or one 32-bit latch. When the
latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs
are latched at the levels set up at the D inputs.

A buffered output-enable (OE

) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.

Copyright  2000, Texas Instruments Incorporated

DOC, EPIC, and Widebus are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN74AVC32373

1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCES327 – APRIL 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.
The SN74AVC32373 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

(each 8-bit latch)

INPUTS

OUTPUT

OE LE D

Q

L H H H
L HL L
L LX Q

0

H X X Z

terminal assignments

1 2 3 4 5 6

A 1Q2 1Q1 1OE 1LE 1D1 1D2
B 1Q4 1Q3 GND GND 1D3 1D4
C 1Q6 1Q5 1V

CC

1V

CC

1D5 1D6

D 1Q8 1Q7 GND GND 1D7 1D8
E 2Q2 2Q1 GND GND 2D1 2D2
F 2Q4 2Q3 1V

CC

1V

CC

2D3 2D4

G 2Q6 2Q5 GND GND 2D5 2D6
H 2Q7 2Q8 2OE 2LE 2D8 2D7
J 3Q2 3Q1 3OE 3LE 3D1 3D2
K 3Q4 3Q3 GND GND 3D3 3D4
L 3Q6 3Q5 2V

CC

2V

CC

3D5 3D6

M 3Q8 3Q7 GND GND 3D7 3D8
N 4Q2 4Q1 GND GND 4D1 4D2
P 4Q4 4Q3 2V

CC

2V

CC

4D3 4D4

R 4Q6 4Q5 GND GND 4D5 4D6
T 4Q7 4Q8 4OE 4LE 4D8 4D7

GKE PACKAGE

(TOP VIEW)

123456

A
B
C
D
E

F
G
H

J

K

L
M
N

P

R

T

SN74AVC32373

1.2-V/3.3-V 32-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS

SCES327 – APRIL 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1OE

1LE

1D1

To Seven Other Channels

1Q1

C1
1D

A3

A4

A5

A2

2OE

2LE

2D1

To Seven Other Channels

2Q1

C1
1D

H3

H4

E5

E2

3OE

3LE

3D1

To Seven Other Channels

3Q1

C1
1D

J3

J4

J5

J2

4OE

4LE

4D1

To Seven Other Channels

4Q1

C1
1D

T3

T4

N5

N2

NOTE A: 1VCC is associated with these channels.

NOTE B: 2VCC is associated with these channels.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high or low state, V

O

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3) 39°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.

3. The package thermal impedance is calculated in accordance with JESD 51.