SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
DOC
(Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V V
D
Overvoltage-Tolerant Inputs/Outputs Allow
CC
Mixed-Voltage-Mode Data Communications
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,
Logic Family T echnology and Applications
Circuitry Technology and Applications
vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
OL
, literature number SCEA006, and
, literature number SCEA009.
D
I
Supports Partial-Power-Down Mode
off
Operation
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
Dynamic Output Control (DOC)
AVC
3.2
2.8
2.4
2.0
1.6
1.2
– Output Voltage – V
OL
0.8
V
0.4
TA = 25°C
Process = Nominal
VCC = 1.8 V
IOL – Output Current – mA
VCC = 2.5 V
VCC = 3.3 V
136
17015311910285685134170
2.8
2.4
2.0
1.6
1.2
– Output Voltage – V
OH
0.8
V
0.4
TA = 25°C
Process = Nominal
VCC = 3.3 V
–128–144–160
IOH – Output Current – mA
VCC = 2.5 V
VCC = 1.8 V
–80–96–112 –32–48–64 0–16
Figure 1. Output Voltage vs Output Current
This 16-bit edge-triggered D-type flip-flop is operational at 1.2-V to 3.6-V VCC, but is designed specifically for
1.65-V to 3.6-V VCC operation.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
description (continued)
The SN74AVC16374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus
drivers, and working registers. It can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive
transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels at the data (D) inputs.
OE
can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly .
The high-impedance state and the increased drive provide the capability to drive bus lines without need for
interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16374 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1CLK
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2CLK
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
. The I
circuitry disables the outputs,
off
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
FUNCTION TABLE
(each 8-bit flip-flop)
INPUTS
CLK D
OE
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
OUTPUT
Q
0
logic symbol
†
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
1EN
2EN
1D
2D
C1
C2
11
12
13
14
16
17
19
20
22
23
2
1Q1
3
1Q2
5
1Q3
6
1Q4
8
1Q5
9
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
1
2
1OE
1CLK
2OE
2CLK
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OE
1CLK
1D1
1
48
47
C1
1D
To Seven Other Channels
2CLK
1Q1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2OE
2D1
24
25
36
C1
1D
To Seven Other Channels
132
2Q1
3
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
O
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCCSuppl
oltage
V
VOOutput voltage
V
I
Static high-level output current
†
mA
I
Static low-level output current
†
mA
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
y v
V
V
V
OHS
OLS
∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V
T
†
Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and V
characteristics. Refer to the TI application reports,
Dynamic Output Control (DOC) Circuitry Technology and Applications
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 3.6 V
I
p
p
p
Operating free-air temperature –40 85 °C
A
AVC Logic Family Technology and Applications
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
Operating 1.4 3.6
Data retention only 1.2
VCC = 1.2 V V
VCC = 1.4 V to 1.6 V 0.65 × V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 1.2 V GND
VCC = 1.4 V to 1.6 V 0.35 × V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
Active state 0 V
3-state 0 3.6
VCC = 1.4 V to 1.6 V –2
VCC = 1.65 V to 1.95 V –4
VCC = 2.3 V to 2.7 V –8
VCC = 3 V to 3.6 V –12
VCC = 1.4 V to 1.6 V 2
VCC = 1.65 V to 1.95 V 4
VCC = 2.3 V to 2.7 V 8
VCC = 3 V to 3.6 V 12
, literature number SCEA009.
CC
CC
0.65 × V
CC
0.35 × V
CC
, literature number SCEA006, and
CC
CC
OH
V
V
vs I
OH
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74AVC16374
Control inputs
V
V
or GND
C
pF
Data inputs
V
V
or GND
CoOut uts
V
O
V
CC
GND
F
(INPUT)
(OUTPUT)
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
I
= –100 µA 1.4 V to 3.6 V VCC–0.2
OHS
I
= –2 mA, VIH = 0.91 V 1.4 V 1.05
OHS
V
OH
V
OL
I
I
off
I
OZ
I
CC
†
Typical values are measured at VCC = 2.5 V and 3.3 V, TA = 25°C.
Control inputs VI = VCC or GND 3.6 V ±2.5 µA
I
p
i
p
p
I
= –4 mA, VIH = 1.07 V 1.65 V 1.2
OHS
I
= –8 mA, VIH = 1.7 V 2.3 V 1.75
OHS
I
= –12 mA, VIH = 2 V 3 V 2.3
OHS
I
= 100 µA 1.4 V to 3.6 V 0.2
OLS
I
= 2 mA, VIL = 0.49 V 1.4 V 0.4
OLS
I
= 4 mA, VIL = 0.57 V 1.65 V 0.45
OLS
I
= 8 mA, VIL = 0.7 V 2.3 V 0.55
OLS
I
= 12 mA, VIL = 0.8 V 3 V 0.7
OLS
VI or VO = 3.6 V 0 ±10 µA
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
=
I
CC
=
I
CC
=
or
V
CC
2.5 V 3
3.3 V 3
2.5 V 2.5
3.3 V 2.5
2.5 V 6.5
3.3 V 6.5
MIN TYP†MAX UNIT
V
V
p
p
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
f
clock
t
w
t
su
t
h
VCC = 1.2 V
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
Clock frequency 160 200 200 MHz
Pulse duration, CLK high or low 3.1 2.5 2.5 ns
Setup time, data before CLK↑ 4.1 2.7 1.9 1.4 1.4 ns
Hold time, data after CLK↑ 1.7 1.3 1.2 1.1 1.1 ns
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
f
max
t
pd
t
en
t
dis
FROM
CLK Q 7.3 1.5 8.4 1.2 6.7 0.8 4.1 0.7 3.3 ns
OE
OE
TO
Q 7.4 1.6 8.5 1.6 6.7 0.9 4.3 0.7 3.4 ns
Q 8.4 2.5 9.4 2.3 7.8 1 4.2 1.5 3.9 ns
VCC = 1.2 V
TYP MIN MAX MIN MAX MIN MAX MIN MAX
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
160 200 200 MHz
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER
TEST CONDITIONS
UNIT
C
C
pF
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
operating characteristics, T
Power dissipation
pd
capacitance
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Timing
Input
Data
Input
Input
Output
CL = 15 pF
(see Note A)
t
PLH
PROPAGATION DELAY TIMES
LOAD CIRCUIT
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
2 kΩ
VCC/2
t
su
VCC/2 VCC/2
= 25°C
A
Outputs enabled
Outputs disabled
V
CC
2 kΩ
t
h
S1
VCC/2
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
= 0,f = 10 MHz
L
= 1.2 V AND 1.5 V ± 0.1 V
2 × V
CC
Open
GND
V
t
PHL
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
S1 at 2 × V
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
t
t
TYP TYP TYP
74 81 89
52 57 63
TEST S1
t
VCC/2
w
Open
2 × V
GND
CC
VCC/2VCC/2
VOL + 0.1 V
VOH – 0.1 V
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
VOLTAGE WAVEFORMS
PULSE DURATION
PZL
VCC/2
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2VCC/2
t
PLZ
t
PHZ
V
0 V
V
0 V
V
V
V
0 V
p
CC
CC
CC
OL
OH
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 1.8 V ± 0.15 V
V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
1 kΩ
1 kΩ
S1
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
500 Ω
500 Ω
S1
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
SN74AVC16374
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
dis
.
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 4. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN74AVC16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES158F – DECEMBER 1998 – REVISED FEBRUARY 2000
PARAMETER MEASUREMENT INFORMATION
= 3.3 V ± 0.3 V
V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
Timing
Input
Data
Input
Input
Output
LOAD CIRCUIT
t
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
t
PLH
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
su
VCC/2
VCC/2
t
h
VCC/2
VCC/2
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
w
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PULSE DURATION
VCC/2
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
VCC/2
t
VOL + 0.3 V
t
VOH – 0.3 V
PLZ
PHZ
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 5. Load Circuit and Voltage Waveforms
10
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