SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
DOC
(Dynamic Output Control) Circuit
Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation
D
Dynamic Drive Capability Is Equivalent to
Standard Outputs With IOH and IOL of
±24 mA at 2.5-V V
CC
D
Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications
D
I
off
Supports Partial-Power-Down Mode
Operation
D
Ideal for Use in PC133 Registered DIMM
Applications
D
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V
OL
vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,
AVC
Logic Family T echnology and Applications
, literature number SCEA006, and
Dynamic Output Control (DOC)
Circuitry Technology and Applications
, literature number SCEA009.
136
–128–144–160
0.4
0.8
1.2
1.6
2.0
2.4
2.8
17015311910285685134170
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2
TA = 25°C
Process = Nominal
IOL – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
– Output Voltage – V
OL
V
TA = 25°C
Process = Nominal
IOH – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
– Output Voltage – V
OH
V
–80–96–112 –32–48–64 0–16
Figure 1. Output Voltage vs Output Current
This 16-bit universal bus driver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to
3.6-V VCC operation.
Data flow from A to Y is controlled by the output-enable (OE
) input. The device operates in the transparent mode
when the latch-enable (LE
) input is low. When LE is high, the A data is latched if the clock (CLK) input is held
at a high or low logic level. If LE is high, the A data is stored in the latch/flip-flop on the low-to-high transition
of CLK. When OE is high, the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
The SN74AVC16334 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
V
CC
Y13
Y14
GND
Y15
Y16
NC
CLK
A1
A2
GND
A3
A4
V
CC
A5
A6
GND
A7
A8
A9
A10
GND
A11
A12
V
CC
A13
A14
GND
A15
A16
LE
NC – No internal connection
FUNCTION TABLE
(each universal bus driver)
INPUTS
OUTPUT
OE LE CLK A
Y
H X X X Z
L LXL L
L LXH H
L H ↑ LL
L H ↑ HH
L H L or H X Y
0
†
†
Output level before the indicated steady-state
input conditions were established
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
1
6
Y4
A1
47
3D
A2
46
A3
44
A4
43
A5
41
A6
40
A7
38
A8
37
A9
36
A10
35
A11
33
A12
32
A13
30
A14
29
A15
27
A16
26
OE
EN1
1
48
CLK
1
2
Y1
3
Y2
5
Y3
8
Y5
9
Y6
11
Y7
12
Y8
13
Y9
14
Y10
16
Y11
17
Y12
19
Y13
20
Y14
22
Y15
23
Y16
C3
25
G2
LE
2C3
1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
48
25
47
1D
C1
CLK
2
To 15 Other Channels
OE
CLK
LE
A1
Y1
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
Operating 1.4 3.6
VCCSuppl
y v
oltage
Data retention only 1.2
V
VCC = 1.2 V V
CC
VCC = 1.4 V to 1.6 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 1.65 V to 1.95 V
0.65 × V
CC
V
VCC = 2.3 V to 2.7 V 1.7
VCC = 3 V to 3.6 V 2
VCC = 1.2 V GND
VCC = 1.4 V to 1.6 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 1.65 V to 1.95 V
0.35 × V
CC
V
VCC = 2.3 V to 2.7 V 0.7
VCC = 3 V to 3.6 V 0.8
V
I
Input voltage 0 3.6 V
p
Active state 0 V
CC
VOOutput voltage
3-state 0 3.6
V
VCC = 1.4 V to 1.6 V –2
p
VCC = 1.65 V to 1.95 V –4
I
OHS
Static high-level output current
†
VCC = 2.3 V to 2.7 V –8
mA
VCC = 3 V to 3.6 V –12
VCC = 1.4 V to 1.6 V 2
p
VCC = 1.65 V to 1.95 V 4
I
OLS
Static low-level output current
†
VCC = 2.3 V to 2.7 V 8
mA
VCC = 3 V to 3.6 V 12
∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V
T
A
Operating free-air temperature –40 85 °C
†
Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and V
OH
vs I
OH
characteristics. Refer to the TI application reports,
AVC Logic Family Technology and Applications
, literature number SCEA006, and
Dynamic Output Control (DOC) Circuitry Technology and Applications
, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
V
CC
MIN TYP†MAX UNIT
I
OHS
= –100 µA 1.4 V to 3.6 V VCC–0.2
I
OHS
= –2 mA, VIH = 0.91 V 1.4 V 1.05
V
OH
I
OHS
= –4 mA, VIH = 1.07 V 1.65 V 1.2
V
I
OHS
= –8 mA, VIH = 1.7 V 2.3 V 1.75
I
OHS
= –12 mA, VIH = 2 V 3 V 2.3
I
OLS
= 100 µA 1.4 V to 3.6 V 0.2
I
OLS
= 2 mA, VIL = 0.49 V 1.4 V 0.4
V
OL
I
OLS
= 4 mA, VIL = 0.57 V 1.65 V 0.45
V
I
OLS
= 8 mA, VIL = 0.7 V 2.3 V 0.55
I
OLS
= 12 mA, VIL = 0.8 V 3 V 0.7
I
I
Control inputs VI = VCC or GND 3.6 V ±2.5 µA
I
off
VI or VO = 3.6 V 0 ±10 µA
I
OZ
VO = VCC or GND 3.6 V ±10 µA
I
CC
VI = VCC or GND, IO = 0 3.6 V 40 µA
p
2.5 V 4
CLK input
V
I
=
V
CC
or GND
3.3 V 4
p
2.5 V 4
p
CiControl inputs
V
I
=
V
CC
or GND
3.3 V 4
pF
p
2.5 V 2.5
Data inputs
V
I
=
V
CC
or
GND
3.3 V 2.5
p
2.5 V 6.5
p
CoOut uts
V
O
=
V
CC
or
GND
3.3 V 6.5
F
†
Typical values are measured at TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 2 through 5)
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX
f
clock
Clock frequency 150 150 150 MHz
Pulse
LE low 3.3 3.3 3.3
t
w
duration
CLK high or low
3.3 3.3 3.3
ns
Data before CLK↑ 1 0.8 0.7 0.7 0.7
t
su
Setup
Data
CLK high 1.5 1.4 0.9 0.9 0.9
ns
time
before LE↑
CLK low 2.7 1.6 1.2 1 1
t
h
Hold
time
Data after CLK↑ 1.3 1.1 0.9 0.8 0.7 ns
Hold Data
CLK high 2.2 1.9 1.7 1.5 1.5 ns
t
h
time after LE↑
CLK low 2.4 1.8 1.6 1.4 1.3 ns
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
TO
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
f
max
150 150 150 MHz
A 5.3 1.2 6.2 1.5 4.9 1 3.2 0.9 2.5
t
pd
LE
Y
7 2.2 9.7 1.8 7.5 1.5 4.9 0.8 4
ns
CLK 6 1.9 7.8 1.6 6 1.1 3.7 1 3.1
t
en
OE Y 7.9 2.4 10.2 1.6 8.8 1.5 6.7 1 6.2 ns
t
dis
OE Y 7.7 2.1 10.3 1.5 8.4 1.2 5.3 1 5.3 ns
switching characteristics, TA = 0°C to 85°C, CL = 0 pF
†
PARAMETER
FROM
TO
VCC = 3.3 V
± 0.15 V
UNIT
(INPUT)
(OUTPUT)
MIN MAX
A
0.6 1.3
t
p
d
CLK
Y
0.7 1.5
ns
†
Texas Instruments SPICE simulation data
operating characteristics, T
A
= 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
TYP TYP TYP
UNIT
Power dissipation
Outputs enabled
45 48 52
p
C
pd
capacitance
Outputs disabled
C
L
=
0
,f = 10 MHz
23 25 28
pF
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.2 V AND 1.5 V ± 0.1 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 15 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
2 kΩ
2 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.1 V
VOH – 0.1 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 2. Load Circuit and Voltage Waveforms
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 3. Load Circuit and Voltage Waveforms
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 4. Load Circuit and Voltage Waveforms
SN74AVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES154G – DECEMBER 1998 – REVISED FEBRUARY 2000
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 3.3 V ± 0.3 V
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
V
OH
V
OL
0 V
VOL + 0.3 V
VOH – 0.3 V
0 V
V
CC
0 V
0 V
V
CC
0 V
t
w
Input
V
CC
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
VCC/2
Figure 5. Load Circuit and Voltage Waveforms
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