How it Works
Datasheet
Loading...
SN74AVC16245DGVR

Datasheet SN74AVC16245DGGR, SN74AVC16245DGVR Datasheet (Texas Instruments)

Download
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SN74A VC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
1
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
DOC
(Dynamic Output Control) Circuit
Dynamically Changes Output Impedance, Resulting in Noise Reduction Without Speed Degradation
D
Less Than 2-ns Maximum Propagation Delay at 2.5-V and 3.3-V V
CC
D
Dynamic Drive Capability Is Equivalent to Standard Outputs With I
OH
and IOL of
±24 mA at 2.5-V V
CC
D
Overvoltage-Tolerant Inputs/Outputs Allow Mixed-Voltage-Mode Data Communications
D
I
off
Supports Partial-Power-Down Mode
Operation
D
ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A)
D
Latch-Up Performance Exceeds 250 mA Per JESD 78
D
Package Options Include Plastic Thin Shrink Small-Outline (DGG) and Thin Very Small-Outline (DGV) Packages
description
A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1 shows typical V
OL
vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,
AVC
Logic Family T echnology and Applications
, literature number SCEA006, and
Dynamic Output Control (DOC)
Circuitry Technology and Applications
, literature number SCEA009.
136
–128–144–160
0.4
0.8
1.2
1.6
2.0
2.4
2.8
17015311910285685134170
0.4
0.8
1.2
1.6
2.0
2.4
2.8
3.2 TA = 25°C
Process = Nominal
IOL – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
– Output Voltage – V
OL
V
TA = 25°C Process = Nominal
IOH – Output Current – mA
VCC = 3.3 V
VCC = 2.5 V
VCC = 1.8 V
– Output Voltage – V
OH
V
–80–96–112 –32–48–64 0–16
Figure 1. Output Voltage vs Output Current
This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed specifically for 1.65-V to 3.6-V VCC operation.
The SN74A VC16245 is designed for asynchronous communication between data buses. The control-function implementation minimizes external timing requirements.
This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 2000, Texas Instruments Incorporated
DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.
SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
2
description (continued)
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I
off
. The I
off
circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down. The SN74AVC16245 is characterized for operation from –40°C to 85°C.
terminal assignments
DGG OR DGV PACKAGE
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
1DIR
1B1 1B2
GND
1B3 1B4
V
CC
1B5 1B6
GND
1B7 1B8 2B1 2B2
GND
2B3 2B4
V
CC
2B5 2B6
GND
2B7 2B8
2DIR
1OE 1A1 1A2 GND 1A3 1A4 V
CC
1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 V
CC
2A5 2A6 GND 2A7 2A8 2OE
FUNCTION TABLE
(each 8-bit transceiver)
INPUTS
OE DIR
OPERATION
L L B data to A bus L H A data to B bus H X Isolation
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
3
logic symbol
†
1A2
46
1A3
44
1A4
43
1A5
41
1A6
40
1A7
38
1A8
37
2A2
35
2A3
33
2A4
32
2A5
30
2A6
29
2A7
27
2A8
26
1OE
2OE
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
1A1
47
G3
48
3 EN1 [BA]
1
1DIR
3 EN2 [AB] G6
25
6 EN4 [BA]
24
2DIR
6 EN5 [AB]
1B1
2
1B2
3
1B3
5
1B4
6
1B5
8
1B6
9
1B7
11
1B8
12
2A1
36
2B1
13
2B2
14
2B3
16
2B4
17
2B5
19
2B6
20
2B7
22
2B8
23
1
2
4
5
logic diagram (positive logic)
To Seven Other Channels
1DIR
1A1
1B1
1OE
To Seven Other Channels
2DIR
2A1
2B1
2OE
1
47
24
36
48
2
25
13
SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any input/output
when the output is in the high-impedance or power-off state, V
O
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . .
Voltage range applied to any input/output
when the output is in the high or low state, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.
3. The package thermal impedance is calculated in accordance with JESD 51.
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
5
recommended operating conditions (see Note 4)
MIN MAX UNIT
pp
Operating 1.4 3.6
VCCSuppl
y v
oltage
Data retention only 1.2
V
VCC = 1.2 V V
CC
VCC = 1.4 V to 1.6 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 1.65 V to 1.95 V
0.65 × V
CC
V VCC = 2.3 V to 2.7 V 1.7 VCC = 3 V to 3.6 V 2 VCC = 1.2 V GND VCC = 1.4 V to 1.6 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 1.65 V to 1.95 V
0.35 × V
CC
V VCC = 2.3 V to 2.7 V 0.7 VCC = 3 V to 3.6 V 0.8
V
I
Input voltage 0 3.6 V
p
Active state 0 V
CC
VOOutput voltage
3-state 0 3.6
V
VCC = 1.4 V to 1.6 V –2
p
VCC = 1.65 V to 1.95 V –4
I
OHS
Static high-level output current
†
VCC = 2.3 V to 2.7 V –8
mA
VCC = 3 V to 3.6 V –12 VCC = 1.4 V to 1.6 V 2
p
VCC = 1.65 V to 1.95 V 4
I
OLS
Static low-level output current
†
VCC = 2.3 V to 2.7 V 8
mA
VCC = 3 V to 3.6 V 12
∆t/∆v Input transition rise or fall rate VCC = 1.4 V to 3.6 V 5 ns/V T
A
Operating free-air temperature –40 85 °C
†
Dynamic drive capability is equivalent to standard outputs with IOH and IOL of ±24 mA at 2.5-V VCC. See Figure 1 for VOL vs IOL and VOH vs IOH characteristics. Refer to the TI application reports,
AVC Logic Family T echnology and Applications
, literature number SCEA006,
and
Dynamic Output Control (DOC) Circuitry Technology and Applications
, literature number SCEA009.
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
6
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
V
CC
MIN TYP†MAX UNIT
I
OHS
= –100 µA 1.4 V to 3.6 V VCC–0.2
I
OHS
= –2 mA, VIH = 0.91 V 1.4 V 1.05
V
OH
I
OHS
= –4 mA, VIH = 1.07 V 1.65 V 1.2
V
I
OHS
= –8 mA, VIH = 1.7 V 2.3 V 1.75
I
OHS
= –12 mA, VIH = 2 V 3 V 2.3
I
OLS
= 100 µA 1.4 V to 3.6 V 0.2
I
OLS
= 2 mA, VIL = 0.49 V 1.4 V 0.4
V
OL
I
OLS
= 4 mA, VIL = 0.57 V 1.65 V 0.45
V
I
OLS
= 8 mA, VIL = 0.7 V 2.3 V 0.55
I
OLS
= 12 mA, VIL = 0.8 V 3 V 0.7
I
I
Control inputs VI = VCC or GND 3.6 V ±2.5 µA
I
off
VI or VO = 3.6 V 0 ±10 µA
I
OZ
‡
VO = VCC or GND, VI (OE)= V
CC
3.6 V ±12.5 µA
I
CC
VI = VCC or GND, IO = 0 3.6 V 40 µA
p
2.5 V 3 p
CiControl inputs
V
I
=
V
CC
or GND
3.3 V 3
pF
p
2.5 V 9 p
C
i
o
A or B orts
V
O
=
V
CC
or
GND
3.3 V 9
F
†
Typical values are measured at TA = 25°C.
‡
For I/O ports, the parameter IOZ includes the input leakage current.
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 2 through 5)
PARAMETER
FROM
TO
VCC = 1.2 V
VCC = 1.5 V
± 0.1 V
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
TYP MIN MAX MIN MAX MIN MAX MIN MAX
t
pd
A or B B or A 3.9 0.8 4 0.7 3 0.6 1.9 0.5 1.7 ns
t
en
OE
A or B 8.4 1.5 9.2 1.4 7 1 4.3 0.7 3.7 ns
t
dis
OE
A or B 8.4 2.3 9.3 2.2 7 1.1 4 1.2 3.9 ns
operating characteristics, T
A
= 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
PARAMETER
TEST CONDITIONS
TYP TYP TYP
UNIT
Power dissipation
Outputs enabled
35 38 44
p
C
pd
capacitance
Outputs disabled
C
L
= 0,f = 10 MHz
6 6 7
pF
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
7
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.2 V AND 1.5 V ± 0.1 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
2 kΩ
2 kΩ
Output
Control (low-level enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.1 V
VOH – 0.1 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 2. Load Circuit and Voltage Waveforms
SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
8
PARAMETER MEASUREMENT INFORMATION
V
CC
= 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
1 kΩ
1 kΩ
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 3. Load Circuit and Voltage Waveforms
SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
9
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Output
Control (low-level enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 4. Load Circuit and Voltage Waveforms
SN74AVC16245 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000
10
PARAMETER MEASUREMENT INFORMATION
V
CC
= 3.3 V ± 0.3 V
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
V
OH
V
OL
0 V
VOL + 0.3 V
VOH – 0.3 V
0 V
V
CC
0 V
0 V
V
CC
0 V
t
w
Input
V
CC
V
CC
V
CC
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WA VEFORMS
PULSE DURATION
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns. D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
Figure 5. Load Circuit and Voltage Waveforms
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
Loading...
Buy Points How it Works FAQ Contact Us Questions and Suggestions Privacy Policy Cookie Policy Terms of Use