Texas Instruments SN74AVC16245DGGR, SN74AVC16245DGVR Datasheet

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SN74A VC16245

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

DOC

 (Dynamic Output Control) Circuit

Dynamically Changes Output Impedance,
Resulting in Noise Reduction Without
Speed Degradation

D

Less Than 2-ns Maximum Propagation
Delay at 2.5-V and 3.3-V V

CC

D

Dynamic Drive Capability Is Equivalent to
Standard Outputs With I

OH

and IOL of

±24 mA at 2.5-V V

CC

D

Overvoltage-Tolerant Inputs/Outputs Allow
Mixed-Voltage-Mode Data Communications

D

I

off

Supports Partial-Power-Down Mode

Operation

D

ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 78

D

Package Options Include Plastic Thin
Shrink Small-Outline (DGG) and Thin Very
Small-Outline (DGV) Packages

description

A Dynamic Output Control (DOC) circuit is implemented, which, during the transition, initially lowers the output
impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Figure 1
shows typical V

OL

vs IOL and VOH vs IOH curves to illustrate the output impedance and drive capability of the
circuit. At the beginning of the signal transition, the DOC circuit provides a maximum dynamic drive that is
equivalent to a high-drive standard-output device. For more information, refer to the TI application reports,

AVC

Logic Family T echnology and Applications

, literature number SCEA006, and

Dynamic Output Control (DOC)

Circuitry Technology and Applications

, literature number SCEA009.

136

–128–144–160

0.4

0.8

1.2

1.6

2.0

2.4

2.8

17015311910285685134170

0.4

0.8

1.2

1.6

2.0

2.4

2.8

3.2
TA = 25°C

Process = Nominal

IOL – Output Current – mA

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

– Output Voltage – V

OL

V

TA = 25°C
Process = Nominal

IOH – Output Current – mA

VCC = 3.3 V

VCC = 2.5 V

VCC = 1.8 V

– Output Voltage – V

OH

V

–80–96–112 –32–48–64 0–16

Figure 1. Output Voltage vs Output Current

This 16-bit (dual octal) noninverting bus transceiver is operational at 1.2-V to 3.6-V VCC, but is designed
specifically for 1.65-V to 3.6-V VCC operation.

The SN74A VC16245 is designed for asynchronous communication between data buses. The control-function
implementation minimizes external timing requirements.

This device can be used as two 8-bit transceivers or one 16-bit transceiver. It allows data transmission from the
A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR)
input. The output-enable (OE) input can be used to disable the device so that the buses are effectively isolated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Copyright  2000, Texas Instruments Incorporated

DOC, EPIC, and Widebus are trademarks of Texas Instruments Incorporated.

SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.
The SN74AVC16245 is characterized for operation from –40°C to 85°C.

terminal assignments

DGG OR DGV PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1DIR

1B1
1B2

GND

1B3
1B4

V

CC

1B5
1B6

GND

1B7
1B8
2B1
2B2

GND

2B3
2B4

V

CC

2B5
2B6

GND

2B7
2B8

2DIR

1OE
1A1
1A2
GND
1A3
1A4
V

CC

1A5
1A6
GND
1A7
1A8
2A1
2A2
GND
2A3
2A4
V

CC

2A5
2A6
GND
2A7
2A8
2OE

FUNCTION TABLE

(each 8-bit transceiver)

INPUTS

OE DIR

OPERATION

L L B data to A bus
L H A data to B bus
H X Isolation

SN74AVC16245

16-BIT BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

1A2

46

1A3

44

1A4

43

1A5

41

1A6

40

1A7

38

1A8

37

2A2

35

2A3

33

2A4

32

2A5

30

2A6

29

2A7

27

2A8

26

1OE

2OE

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

1A1

47

G3

48

3 EN1 [BA]

1

1DIR

3 EN2 [AB]
G6

25

6 EN4 [BA]

24

2DIR

6 EN5 [AB]

1B1

2

1B2

3

1B3

5

1B4

6

1B5

8

1B6

9

1B7

11

1B8

12

2A1

36

2B1

13

2B2

14

2B3

16

2B4

17

2B5

19

2B6

20

2B7

22

2B8

23

1

2

4

5

logic diagram (positive logic)

To Seven Other Channels

1DIR

1A1

1B1

1OE

To Seven Other Channels

2DIR

2A1

2B1

2OE

1

47

24

36

48

2

25

13

SN74AVC16245
16-BIT BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES142L – JULY 1998 – REVISED FEBRUAR Y 2000

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any input/output

when the output is in the high-impedance or power-off state, V

O

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . .

Voltage range applied to any input/output

when the output is in the high or low state, V

O

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θJA (see Note 3): DGG package 70°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 58°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.

3. The package thermal impedance is calculated in accordance with JESD 51.