TEXAS INSTRUMENTS SN74AUC2G53 Technical data

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DCT OR DCU PACKAGE

(TOP VIEW)

1 2 3 4

8 7 6 5

COM

INH GND GND

V

CC

Y1 Y2 A

4 3 2 1

5 6 7 8

GND GND

INH

COM

A Y2 Y1 V

CC

YEP OR YZP PACKAGE

(BOTTOM VIEW)

查询SN74AUC2G53供应商

SN74AUC2G53

SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR

2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

FEATURES

• Available in the Texas Instruments

NanoStar™ and NanoFree™ Packages

• Operates at 0.8 V to 2.7 V

• Sub-1-V Operable

• Low Power Consumption, 10 µ A at 2.7 V

• High On-Off Output Voltage Ratio

• High Degree of Linearity

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

This analog switch is operational at 0.8-V to 2.7-V V operation.

The SN74AUC2G53 can handle both analog and digital signals. The device permits signals with amplitudes of up to V

(peak) to be transmitted in either direction.

CC

NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.

Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.

, but is designed specifically for 1.1-V to 2.7-V V

CC

–40°C to 85°C

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.

DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ⋅ = Pb-free).

NanoStar, NanoFree are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

ORDERING INFORMATION

T

A

NanoStar™ – WCSP (DSBGA)

0.23-mm Large Bump – YEP NanoFree™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP (Pb-free) SSOP – DCT Tape and reel SN74AUC2G53DCTR U53_ _ _ VSSOP – DCU Tape and reel SN74AUC2G53DCUR U53_

PACKAGE

(1)

Tape and reel _ _ _U4_

ORDERABLE PART NUMBER TOP-SIDE MARKING

SN74AUC2G53YEPR

SN74AUC2G53YZPR

FUNCTION TABLE

CONTROL

INPUTS

INH A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

L L Y1 L H Y2

H X None

ON

CHANNEL

(2)

www.ti.com

Y2

A

INH

Y1

COM

5

2

7

6

1

SW

NOTE A: For simplicity, the test conditions shown in Figures 1 through 4 and 6 through 10 are for the demultiplexer configuration. Signals may

be passed from COM to Y1 (Y2) or from Y1 (Y2) to COM.

COM Y

SN74AUC2G53 SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

LOGIC DIAGRAM (POSITIVE LOGIC)

SIMPLIFIED SCHEMATIC, EACH SWITCH (SW)

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

V

CC

V

I

V

I/O

I

IK

I

I/OK

I

T

Supply voltage range Input voltage range Switch I/O voltage range Control input clamp current VI< 0 –50 mA I/O port diode current V On-state switch current current V Continuous current through V

θ

JA

T

stg

Package thermal impedance

Storage temperature range –65 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltages are with respect to ground unless otherwise specified. (3) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (4) The package thermal impedance is calculated in accordance with JESD 51-7.

2

(2)

(2) (3)

(1)

MIN MAX UNIT

–0.5 3.6 V –0.5 3.6 V

(2) (3)

< 0 or V

I/O

= 0 to V

I/O

or GND ±100 mA

CC

> V

I/O

CC

–0.5 V

DCT package 220

(4)

DCU package 227 °C/W YEP/YZP package 102

+ 0.5 V

CC

±50 mA ±50 mA

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SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR

Recommended Operating Conditions

V

V V

∆ t/ ∆ v Input transition rise or fall rate V

T

(1) All unused inputs of the device must be held at V

Supply voltage 0.8 2.7 V

CC

High-level input voltage V

IH

Low-level input voltage V

IL

I/O port voltage 0 V

I/O

Control input voltage 0 3.6 V

I

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

(1)

or GND to ensure proper device operation. Refer to the TI application report,

CC

2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

MIN MAX UNIT

V

= 0.8 V V

CC

= 1.1 V to 1.95 V 0.65 × V

CC

V

= 2.3 V to 2.7 V 1.7

CC

V

= 0.8 V 0

CC

= 1.1 V to 1.95 V 0.35 × V

CC

V

= 2.3 V to 2.7 V 0.7

CC

V

= 0.8 V to 1.6 V 20

CC

= 1.65 V to 1.95 V 10 ns/V

CC

V

= 2.3 V to 2.7 V 3.5

CC

CC CC

SN74AUC2G53

V

CC

V

CC

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

r

on

r

on(p)

∆ r

on

I

S(off)

I

S(on)

I

CC

C

ic

C

io(off)

C

io(on)

(1) TA= 25°C

VI= V

On-state switch resistance Ω

V (see Figure 1 and Figure 2 )

VI= V

Peak on resistance Ω

V (see Figure 1 and Figure 2 )

VI= V Difference of on-state resistance VC= V between switches (see Figure 1 and

Figure 2 )

VI= V Off-state switch leakage current VI= GND and VO= VCC, 2.7 V µ A

V

On-state switch leakage current 2.7 V µ A

VI= V

VO= Open (see Figure 4 ) Control input current VC= V

Supply current VC= V Control input capacitance 2.5 V 2 pF

Switch input/output capacitance 2.5 V pF

Y 3 COM 4.5

Switch input/output capacitance 2.5 V 9 pF

or GND, 1.1 V 40

CC

= V

INH

IL

to GND, 1.1 V 131 180

CC

= V

INH

IL

to GND, 1.1 V 4

CC

IH

and VO= GND, or ±1

CC

= VIH(see Figure 3 )

INH

or GND, V

CC

or GND 2.7 V ±5 µ A

CC

or GND 2.7 V 10 µ A

CC

INH

MIN TYP

IS= 4 mA

CC

1.65 V 12.5 20

IS= 8 mA 2.3 V 6 15

IS= 4 mA

1.65 V 32 80

IS= 8 mA 2.3 V 15 20

IS= 4 mA

1.65 V 1

IS= 8 mA 2.3 V 1

= VIL,

(1)

MAX UNIT

Ω

(1)

±0.1

±1

(1)

±0.1

3

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SN74AUC2G53 SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

Switching Characteristics

over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 5 )

V

= 1.2 V V

V

= 0.8 V

PARAMETER UNIT

(1)

t

pd

t

en

t

dis

t

en

t

dis

FROM TO

(INPUT) (OUTPUT)

COM or Y Y or COM 0.3 0.3 0.3 0.2 0.1 ns

INH COM or Y ns

A COM or Y ns

CC

TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX

9.2 0.5 3.5 0.5 2.2 0.5 1 1.9 0.5 1.8

8.1 0.5 4.2 0.5 3.2 0.5 1.9 3.4 0.5 2.6

9.2 0.5 3.6 0.5 2.3 0.5 1.1 1.9 0.5 1.6 10 0.5 3.6 0.5 2.3 0.5 1.1 2 0.5 1.6

CC

± 0.1 V ± 0.1 V ± 0.15 V ± 0.2 V

(1) The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load

capacitance, when driven by an ideal voltage source (zero output impedance).

Switching Characteristics

over recommended operating free-air temperature range, CL= 30 pF (unless otherwise noted) (see Figure 5 )

PARAMETER UNIT

(1)

t

pd

t

en

t

dis

t

en

t

dis

FROM TO

(INPUT) (OUTPUT)

COM or Y Y or COM 0.4 0.2 ns

INH COM or Y ns

A COM or Y ns

= 1.5 V V

CC

= 1.8 V V

CC

V

= 1.8 V V

CC

± 0.15 V ± 0.2 V

CC

MIN TYP MAX MIN MAX

0.5 1.6 3.1 0.5 2.2

0.5 2.2 3.4 0.5 2.2

0.5 1.6 3 0.5 2.2

0.5 1.6 3 0.5 2.3

= 2.5 V

(1) The propagation delay is the calculated RC time constant of the typical on-state resistance of the switch and the specified load

capacitance, when driven by an ideal voltage source (zero output impedance).

Analog Switch Characteristics

TA= 25°C

PARAMETER TEST CONDITIONS V

Frequency response

(1)

(switch ON)

(1) Adjust finvoltage to obtain 0 dBm at output. Increase finfrequency until dB meter reads –3 dB.

FROM TO

(INPUT) (OUTPUT)

CC

0.8 V 90

CL= 50 pF, RL= 600 Ω ,

1.1 V 101

fin= sine wave 1.4 V 110 (see Figure 6 )

COM or Y Y or COM MHz

CL= 5 pF, RL= 50 Ω ,

1.65 V 122

2.3 V 198

0.8 V >500

1.1 V >500

fin= sine wave 1.4 V >500 (see Figure 6 )

1.65 V >500

2.3 V >500

TYP UNIT

4

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SN74AUC2G53

SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR

2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

Analog Switch Characteristics (continued)

TA= 25°C

PARAMETER TEST CONDITIONS V

Crosstalk (between switches)

Crosstalk fin= 1 MHz (square (control input to signal output) wave)

Feed-through attenuation (switch OFF)

Sine-wave distortion COM or Y Y or COM %

(2)

FROM TO

(INPUT) (OUTPUT)

CL= 50 pF, RL= 600 Ω , fin= 1 MHz (sine wave) 1.4 V –59 (see Figure 7 )

COM or Y Y or COM dB

CL= 5 pF, RL= 50 Ω , fin= 1 MHz (sine wave) 1.4 V –55 (see Figure 7 )

CL= 50 pF, RL= 600 Ω ,

INH COM or Y 1.4 V 0.81 mV

(see Figure 8 )

CL= 50 pF, RL= 600 Ω , fin= 1 MHz (sine wave) 1.4 V –60 (see Figure 9 )

COM or Y Y or COM dB

CL= 5 pF, RL= 600 Ω , fin= 1 MHz (sine wave) 1.4 V –59 (see Figure 9 )

CL= 50 pF, RL= 10 k Ω , fin= 1 kHz (sine wave) 1.4 V 0.06 (see Figure 10 )

CL= 50 pF, RL= 10 k Ω , fin= 10 kHz (sine wave) 1.4 V 0.04 (see Figure 10 )

CC

0.8 V –59

1.1 V –59

1.65 V –59

2.3 V –60

0.8 V –55

1.1 V –55

1.65 V –55

2.3 V –55

0.8 V 0.56

1.1 V 0.68

1.65 V 0.93

2.3 V 1.5

0.8 V –60

1.1 V –60

1.65 V –60

2.3 V –60

0.8 V –59

1.1 V –59

1.65 V –59

2.3 V –59

0.8 V 6.19

1.1 V 0.39

1.65 V 0.02

2.3 V 0.01

0.8 V 3.55

1.1 V 0.38

1.65 V 0.02

2.3 V 0.02

TYP UNIT

(2) Adjust finvoltage to obtain 0 dBm at input.

Operating Characteristics

for INH input, TA= 25°C

PARAMETER UNIT

Power dissipation

C

pd

capacitance

V

= 0.8 V V

TEST

CONDITIONS

f = 10 MHz 3 3 3 3 3 pF

CC

TYP TYP TYP TYP TYP

= 1.2 V V

CC

= 1.5 V V

CC

= 1.8 V V

CC

= 2.5 V

CC

5

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SN74AUC2G53 SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

Operating Characteristics

for A input, TA= 25°C

V

= 0.8 V V

PARAMETER UNIT

Power

C

dissipation f = 10 MHz pF

pd

capacitance

Outputs enabled

Outputs disabled

TEST

CONDITIONS

CC

TYP TYP TYP TYP TYP

5.5 5.5 5.5 5.5 5.5

0.5 0.5 0.5 0.5 0.5

= 1.2 V V

CC

= 1.5 V V

CC

= 1.8 V V

CC

= 2.5 V

CC

6

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V

CC

VI = V

CC

or GND

V

O

r

on



VI V

O

I

S



V

I

- V

O

GND

V

Y1

I

S

(On)

V

CC

V

IL

Y2

A V

A

V

INH

COM

VIL or V

IH

S 1 2

V

A

V

IL

V

IH

S

1

2

0

20

40

60

80

100

120

0 1 2 3

VCC = 1.65 V

VCC = 1.1 V

VCC = 2.3 V

SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR

PARAMETER MEASUREMENT INFORMATION

SN74AUC2G53

2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

Figure 1. On-State Resistance Test Circuit

Figure 2. Typical ronas a Function of Voltage (V

) for VI= 0 to V

I

CC

7

www.ti.com

V

CC

V

I

V

O

GND

Y1

(Off)

V

CC

V

IH

Y2

A V

A

V

INH

COM

VIL or V

IH

S 1 2

V

A

V

IL

V

IH

S

1

2

A

Condition 1: VI = GND, VO = V

CC

Condition 2: VI = VCC, VO = GND

V

CC

V

I

V

O

GND

Y1

(On)

V

CC

V

IL

Y2

A V

A

V

INH

COM

VIL or V

IH

S 1 2

V

A

V

IL

V

IH

S

1

2

A

V

I

= VCC or GND

V

O

= Open

SN74AUC2G53 SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

Figure 3. Off-State Switch Leakage-Current Test Circuit

Figure 4. On-State Switch Leakage-Current Test Circuit

8

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V

M

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

V

LOAD

Open

GND

R

L

R

L

Data Input

Timing Input

V

I

0 V

V

I

0 V

t

w

Input

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

PULSE DURATION

t

PLH

t

PHL

t

PHL

t

PLH

V

OH

V

OH

V

OL

V

OL

V

I

0 V

Input

Output Waveform 1 S1 at V

LOAD

(see Note B)

Output Waveform 2

S1 at GND

(see Note B)

V

OL

V

OH

t

PZL

t

PZH

t

PLZ

t

PHZ

V

LOAD

/2

0 V

VOL + V

∆

VOH − V

∆

≈0 V

V

I

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

Output

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, slew rate ≥ 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

Output

Control

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

I

V

M

V

M

0.8 V

1.2 V ± 0.1 V

1.5 V ± 0.1 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

2 kΩ 2 kΩ 2 kΩ 2 kΩ 2 kΩ 1 kΩ

500 Ω

V

CC

R

L

2 × V

CC

2 × V

CC

2 × V

CC

2 × V

CC

2 × V

CC

2 × V

CC

2 × V

CC

V

LOAD

C

L

15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF

0.1 V

0.15 V

V

∆

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

I

VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2 VCC/2

V

M

tr/t

f

≤2 ns ≤2 ns ≤2 ns ≤2 ns ≤2 ns ≤2 ns ≤2 ns

INPUTS

SN74AUC2G53

SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR

2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

Figure 5. Load Circuit and Voltage Waveforms

9

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V

CC

V

O

GND

Y1

(On)

V

CC

V

IL

Y2

A V

A

V

INH

COM

VIL or V

IH

S 1 2

V

A

V

IL

V

IH

S

1

2

50 Ω

0.1 µF

f

in

RL/CL: 600 Ω/50 pF RL/CL: 50 Ω/5 pF

R

L

C

L

VCC/2

V

CC

V

O1

GND

Y1

V

CC

V

IL

Y2

VIL or V

IH

50 Ω

0.1 µF

f

in

C

L

50 pF

VCC/2

R

in

600 Ω

R

L

600 Ω

V

O2

C

L

50 pF

VCC/2

R

L

600 Ω

V

A

V

IL

V

IH

TEST CONDITION

20log10(VO2/VI) 20log10(VO1/VI)

A V

A

V

INH

COM

SN74AUC2G53 SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

10

Figure 6. Frequency Response (Switch On)

Figure 7. Crosstalk (Between Switches)

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V

CC

V

O

GND

Y1

(On)

V

CC

Y2

VIL or V

IH

S 1 2

V

A

V

IL

V

IH

S

1

2

50 Ω

VCC/2

R

in

600 Ω

VCC/2

C

L

50 pF

R

L

600 Ω

A V

A

V

INH

COM

V

CC

V

O

GND

Y1

(Off)

V

CC

V

IL

Y2

VIL or V

IH

S

1

2

50 Ω

0.1 µF

f

in

RL/CL: 600 Ω/50 pF RL/CL: 50 Ω/5 pF

R

L

C

L

VCC/2

R

L

VCC/2

A V

A

V

INH

COM

S 1 2

V

A

V

IL

V

IH

SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR

PARAMETER MEASUREMENT INFORMATION

SN74AUC2G53

2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

Figure 8. Crosstalk (Control Input, Switch Output)

Figure 9. Feedthrough (Switch Off)

11

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V

CC

V

O

GND

Y1

(On)

V

CC

V

IL

Y2

VIL or V

IH

S 1 2

V

A

V

IL

V

IH

S

1

2

600 Ω

10 µF

f

in

R

L

10 kΩ

C

L

50 pF

VCC/2

10 µF

A V

A

V

INH

COM

VCC = 0.8 V , VI = 0.7 V

P-P

VCC = 1.1 V , V

I

= 1 V

P-P

VCC = 1.4 V , V

I

= 1.2 V

P-P

VCC = 1.65 V , VI = 1.4 V

P-P

VCC = 2.3 V , VI = 2 V

P-P

SN74AUC2G53 SINGLE-POLE DOUBLE-THROW (SPDT) ANALOG SWITCH OR 2:1 ANALOG MULTIPLEXER/DEMULTIPLEXER

SCES484A – AUGUST 2003 – REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

Figure 10. Sine-Wave Distortion

12

PACKAGE OPTION ADDENDUM

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6-Jun-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

SN74AUC2G53DCTR ACTIVE SM8 DCT 8 3000 Pb-Free

SN74AUC2G53DCUR ACTIVE US8 DCU 8 3000 Pb-Free

SN74AUC2G53DCURE4 ACTIVE US8 DCU 8 3000 Pb-Free

SN74AUC2G53YEPR ACTIVE WCSP YEP 8 3000 TBD SNPB Level-1-260C-UNLIM SN74AUC2G53YZPR ACTIVE WCSP YZP 8 3000 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period isin effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may notbe available. OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-1-260C-UNLIM

SNAGCU Level-1-260C-UNLIM

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

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Addendum-Page 1

MECHANICAL DATA

MPDS049B – MA Y 1999 – REVISED OCT OBER 2002

DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE P ACKAGE

0,65

PIN 1 INDEX AREA

0,30 0,15

8

1

3,15

2,75

5

2,90 2,70

4

1,30 MAX

M

0,13

4,25 3,75

Seating Plane

0,15 NOM

0° – 8°

Gage Plane

0,25

0,60 0,20

0,10 0,00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion D. Falls within JEDEC MO-187 variation DA.

0,10

4188781/C 09/02

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TEXAS INSTRUMENTS SN74AUC2G53 Technical data

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