TEXAS INSTRUMENTS SN74AUC2G125 Technical data

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FEATURES

DCT OR DCU PACKAGE
(TOP VIEW)
1 2 3 4
8 7 6 5
1OE
GND
V
CC
2OE 1Y 2A
4 3 2 1
5 6 7 8
GND
1OE
CC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
Optimized for 1.8-V Operation and Is 3.6-V I/O
Tolerant to Support Mixed-Mode Signal Operation
I
Sub-1-V Operable
Max tpdof 1.8 ns at 1.8 V
Low Power Consumption, 10 µ A at 1.8 V
±8-mA Output Drive at 1.8 V
Latch-Up Performance Exceeds 100 mA Per
ESD Protection Exceeds JESD 22
Supports Partial-Power-Down Mode
off
Operation
JESD 78, Class II
2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101)
SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES532A – DECEMBER 2003 – REVISED MARCH 2005

DESCRIPTION/ORDERING INFORMATION

This dual bus buffer gate is operational at 0.8-V to 2.7-V V V
operation.
CC
The SN74AUC2G125 features dual line drivers with 3-state outputs. The outputs are disabled when the associated output-enable ( OE) input is high.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
To ensure the high-impedance state during power up or power down, OE should be tied to V resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using I preventing damaging current backflow through the device when it is powered down.
For more information about AUC Little Logic devices, please refer to the TI application report, Applications of Texas Instruments AUC Sub-1-V Little Logic Devices, literature number SCEA027.
–40°C to 85°C
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site. YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
T
, but is designed specifically for 1.65-V to 1.95-V
CC
through a pullup
CC
. The I
off
circuitry disables the outputs,
off
ORDERING INFORMATION
A
NanoStar™ WCSP (DSBGA)
0.23-mm Large Bump YEP NanoFree™ WCSP (DSBGA)
0.23-mm Large Bump YZP (Pb-free) SSOP DCT Tape and reel SN74AUC2G125DCTR U25_ _ _ VSSOP DCU Tape and reel SN74AUC2G125DCUR UM_
PACKAGE
(1)
Tape and reel SN74AUC2G125YEPR
Tape and reel SN74AUC2G125YZPR
ORDERABLE PART NUMBER TOP-SIDE MARKING
_ _ _UM_
(2)
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2003–2005, Texas Instruments Incorporated
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1A 1Y
1OE
1
2 6
2A 2Y
2OE
7
5 3
SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SCES532A – DECEMBER 2003 – REVISED MARCH 2005
FUNCTION TABLE
(EACH BUFFER)
INPUTS
OE A
L H H L L L
H X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
OUTPUT
Y
2
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SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES532A – DECEMBER 2003 – REVISED MARCH 2005

Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
θ
JA
T
stg
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) The package thermal impedance is calculated in accordance with JESD 51-7.
Supply voltage range –0.5 3.6 V Input voltage range Voltage range applied to any output in the high-impedance or power-off state Output voltage range Input clamp current VI< 0 –50 mA Output clamp current VO< 0 –50 mA Continuous output current ±20 mA Continuous current through V
Package thermal impedance
Storage temperature range –65 150 °C
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1)
MIN MAX UNIT
(2)
(2)
(2)
or GND ±100 mA
CC
–0.5 3.6 V –0.5 3.6 V –0.5 V
+ 0.5 V
CC
DCT package 220
(3)
DCU package 227 °C/W YEP/YZP package 102

Recommended Operating Conditions

V
V
V
V
V
I
OH
I
OL
Supply voltage 0.8 2.7 V
CC
High-level input voltage V
IH
Low-level input voltage V
IL
Input voltage 0 3.6 V
I
Output voltage V
O
High-level output current V
Low-level output current V
(1)
t/ v Input transition rise or fall rate V
T
A
(1) All unused inputs of the device must be held at V
Operating free-air temperature –40 85 °C
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
(2) The data was taken at CL= 15 pF, RL= 2 k (see Figure 1 ). (3) The data was taken at CL= 30 pF, RL= 500 (see Figure 1 ).
MIN MAX UNIT
V
= 0.8 V V
CC
= 1.1 V to 1.95 V 0.65 × V
CC
V
= 2.3 V to 2.7 V 1.7
CC
V
= 0.8 V 0
CC
= 1.1 V to 1.95 V 0.35 × V
CC
V
= 2.3 V to 2.7 V 0.7
CC
CC CC
Active state 0 V 3-state 0 3.6 V
= 0.8 V –0.7
CC
V
= 1.1 V –3
CC
= 1.4 V –5 mA
CC
V
= 1.65 V –8
CC
V
= 2.3 V –9
CC
V
= 0.8 V 0.7
CC
V
= 1.1 V 3
CC
= 1.4 V 5 mA
CC
V
= 1.65 V 8
CC
V
= 2.3 V 9
CC
V
= 0.8 V to 1.65 V
CC
= 1.65 V to 1.95 V
CC
V
= 2.3 V to 2.7 V
CC
(2)
(3)
(3)
V
V
CC
CC
20 20 ns/V 15
3
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SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SCES532A – DECEMBER 2003 – REVISED MARCH 2005

Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS V
IOH= –100 µ A 0.8 V to 2.7 V V IOH= –0.7 mA 0.8 V 0.55
V
OH
V
OL
I
I
I
off
I
OZ
I
CC
C C
A or OE inputs VI= V
i o
(1) All typical values are at TA= 25°C.
IOH= –3 mA 1.1 V 0.8 IOH= –5 mA 1.4 V 1 IOH= –8 mA 1.65 V 1.2 IOH= –9 mA 2.3 V 1.8 IOL= 100 µ A 0.8 V to 2.7 V 0.2 IOL= 0.7 mA 0.8 V 0.25 IOL= 3 mA 1.1 V 0.3 IOL= 5 mA 1.4 V 0.4 IOL= 8 mA 1.65 V 0.45 IOL= 9 mA 2.3 V 0.6
or GND 0 to 2.7 V ±5 µ A
CC
VIor VO= 2.7 V 0 ±10 µ A VO= V VI= V VI= V VO= V
or GND 2.7 V ±10 µ A
CC
or GND, IO= 0 0.8 V to 2.7 V 10 µ A
CC
or GND 2.5 V 2.5 pF
CC
or GND 2.5 V 5.5 pF
CC
CC
MIN TYP
0.1
CC
(1)
MAX UNIT
V
V

Switching Characteristics

over recommended operating free-air temperature range, CL= 15 pF (unless otherwise noted) (see Figure 1 )
V
= 1.2 V V
V
= 0.8 V
PARAMETER UNIT
t
pd
t
en
t
dis
FROM TO
(INPUT) (OUTPUT)
A Y 5.1 1 3.6 0.7 2.3 0.6 1 1.8 0.5 1.3 ns OE Y 5.9 1.1 4.1 1 2.6 0.9 1.3 2 0.8 1.5 ns OE Y 6.6 2 4.8 1.5 3.5 1.8 2.6 3.7 1.4 2.9 ns
CC
TYP MIN MAX MIN MAX MIN TYP MAX MIN MAX
CC
± 0.1 V ± 0.1 V ± 0.15 V ± 0.2 V
= 1.5 V V
CC
= 1.8 V V
CC
= 2.5 V
CC

Switching Characteristics

over recommended operating free-air temperature range, CL= 30 pF (unless otherwise noted) (see Figure 1 )
V
= 1.8 V V
PARAMETER UNIT
t
pd
t
en
t
dis
FROM TO
(INPUT) (OUTPUT)
A Y 0.8 1.6 2.6 0.7 1.8 ns OE Y 1.1 1.7 2.9 0.9 2.2 ns OE Y 1.7 2.3 3.6 0.8 2 ns
CC
± 0.15 V ± 0.2 V
MIN TYP MAX MIN MAX
= 2.5 V
CC
4
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Operating Characteristics

TA= 25°C
C
pd
SN74AUC2G125
DUAL BUS BUFFER GATE
WITH 3-STATE OUTPUTS
SCES532A – DECEMBER 2003 – REVISED MARCH 2005
V
= 0.8 V V
PARAMETER UNIT
Power dissipation capacitance
TEST
CONDITIONS
f = 10 MHz 16 16 16 17 18 pF
CC
TYP TYP TYP TYP TYP
= 1.2 V V
CC
= 1.5 V V
CC
= 1.8 V V
CC
= 2.5 V
CC
5
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VCC/2
t
h
t
su
From Output
Under Test
C
L
(see Note A)
LOAD CIRCUIT
S1
2 × V
CC
Open
GND
R
L
R
L
Data Input
Timing Input
V
CC
0 V
V
CC
0 V
0 V
t
w
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
t
PLH
t
PHL
t
PHL
t
PLH
V
OH
V
OH
V
OL
V
OL
V
CC
0 V
Input
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
V
OL
V
OH
t
PZL
t
PZH
t
PLZ
t
PHZ
V
CC
0 V
VOL + V
VOH - V
0 V
V
CC
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Output
Output
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , slew rate 1 V/ns. D. The outputs are measured one at a time, with one transition per measurement. E. t
PLZ
and t
PHZ
are the same as t
dis
.
F. t
PZL
and t
PZH
are the same as ten.
G. t
PLH
and t
PHL
are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Output
Control
VCC/2 VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
VCC/2 VCC/2
VCC/2
VCC/2
VCC/2
V
CC
VCC/2
VCC/2
0.8 V
1.2 V ± 0.1 V
1.5 V ± 0.1 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
1.8 V ± 0.15 V
2.5 V ± 0.2 V
2 k 2 k 2 k 2 k 2 k 1 k
500
V
CC
R
L
0.1 V
0.1 V
0.1 V
0.15 V
0.15 V
0.15 V
0.15 V
V
C
L
15 pF 15 pF 15 pF 15 pF 15 pF 30 pF 30 pF
SN74AUC2G125 DUAL BUS BUFFER GATE WITH 3-STATE OUTPUTS
SCES532A – DECEMBER 2003 – REVISED MARCH 2005

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
6-Jun-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package Drawing
Pins Package
Qty
Eco Plan
74AUC2G125DCURE4 ACTIVE US8 DCU 8 3000 Pb-Free
SN74AUC2G125DCTR ACTIVE SM8 DCT 8 3000 Pb-Free
SN74AUC2G125DCUR ACTIVE US8 DCU 8 3000 Pb-Free
SN74AUC2G125YEPR ACTIVE WCSP YEP 8 3000 TBD SNPB Level-1-260C-UNLIM SN74AUC2G125YZPR ACTIVE WCSP YZP 8 3000 Pb-Free
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(RoHS)
(RoHS)
(RoHS)
(RoHS)
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SNAGCU Level-1-260C-UNLIM
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS049B – MA Y 1999 – REVISED OCT OBER 2002
DCT (R-PDSO-G8) PLASTIC SMALL-OUTLINE P ACKAGE
0,65
PIN 1 INDEX AREA
0,30 0,15
8
1
3,15 2,75
5
2,90 2,70
4
1,30 MAX
M
0,13
4,25 3,75
Seating Plane
0,15 NOM
0° – 8°
Gage Plane
0,25
0,60 0,20
0,10 0,00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion D. Falls within JEDEC MO-187 variation DA.
0,10
4188781/C 09/02
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