Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic (N)
and Ceramic (J) 300-mil DIPs
description
These octal buffers/drivers are designed
specifically to improve both the performance and
density of 3-state memory address drivers, clock
drivers, and bus-oriented receivers and
transmitters. When these devices are used with
the ′ALS241, ′AS241A, ′ALS244, and ′AS244A,
the circuit designer has a choice of selected
combinations of inverting and noninverting
outputs, symmetrical active-low output-enable
(OE
) inputs, and complementary OE and OE
inputs. These devices feature high fan-out and
improved fan-in.
The -1 version of SN74ALS240A is identical to the
standard version, except that the recommended
maximum I
no -1 version of the SN54ALS240A.
for the -1 version is 48 mA. There is
OL
SN54ALS240A, SN54AS240A ...J PACKAGE
SN74ALS240A, SN74AS240A . . . DW OR N PACKAGE
SN54ALS240A, SN54AS240A . . . FK PACKAGE
1A2
2Y3
1A3
2Y2
1A4
(TOP VIEW)
1OE
1
1A1
2
2Y4
3
1A2
4
2Y3
5
1A3
6
2Y2
7
1A4
8
9
2Y1
GND
10
(TOP VIEW)
2Y4
3 2 1 20 19
4
5
6
7
8
910111213
1A1
20
19
18
17
16
15
14
13
12
11
V
1OE
CC
V
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
18
17
16
15
14
CC
1Y1
2A4
1Y2
2A3
1Y3
The SN54ALS240A and SN54AS240A are
characterized for operation over the full military
temperature range of –55°C to 125°C. The
SN74ALS240A and SN74AS240A are
characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each buffer)
INPUTS
OEA
LHL
LLH
HXZ
OUTPUT
Y
2Y1
GND
2A1
1Y4
2A22OE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214C – DECEMBER 1982 – REVISED AUGUST 1995
1
2
4
6
8
19
11
13
15
17
†
EN
EN
logic symbol
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
18
16
14
12
logic diagram (positive logic)
1A1
1A2
1A3
1A4
2A1
2A2
1
2
4
6
8
19
11
13
18
16
14
12
1Y1
1Y2
1Y3
1Y4
9
2Y1
7
2Y2
1OE
1Y1
1Y2
1Y3
1Y4
9
2Y1
7
2Y2
5
2Y3
3
2Y4
2OE
2A3
2A4
15
17
5
2Y3
3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PLZ
FROM
(INPUT)
TO
(OUTPUT)
R1 = 500 Ω
R2 = 500 Ω,
TA = MIN to MAX
SN54AS240ASN74AS240A
MINMAXMINMAX
1716.5
1.26.51.26.5
1716.4
1.19.51.19
1.25.51.25
1.512.51.59.5
,
§
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ALS240A, SN54AS240A, SN74ALS240A, SN74AS240A
OCTAL BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SDAS214C – DECEMBER 1982 – REVISED AUGUST 1995
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
V
CC
R
L
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
Under Test
(see Note A)
Test
Point
C
L
From Output
Under Test
(see Note A)
7 V
RL = R1 = R2
S1
R1
C
L
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
h
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Low-Level
Out-of-Phase
(see Note C)
Pulse
Pulse
Input
In-Phase
Output
Output
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V1.3 V
t
w
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V1.3 V
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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