Texas Instruments JM38510-37201BEA, JM38510-37201B2A, JM38510-37202BEA, JM38510-37202B2A, SN54ALS174J Datasheet
...
D
’ALS174 and ’AS174 Contain Six Flip-Flops
With Single-Rail Outputs
D
’ALS175 and ’AS175B Contain Four
Flip-Flops With Double-Rail Outputs
D
Buffered Clock and Direct-Clear Inputs
D
Applications Include:
– Buffer/Storage Registers
– Shift Registers
– Pattern Generators
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MA Y 1996
D
Fully Buffered Outputs for Maximum
Isolation From External Disturbances
(’AS Only)
D
Package Options Include Plastic
Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
SN54ALS174, SN54AS174 ...J PACKAGE
SN74ALS174, SN74AS174 ...D OR N PACKAGE
SN54ALS174, SN54AS174 . . . FK PACKAGE
1D
2D
NC
2Q
3D
(TOP VIEW)
CLR
1
1Q
2
1D
3
2D
4
2Q
5
3D
6
3Q
7
GND
8
(TOP VIEW)
1Q
3 2 1 20 19
4
5
6
7
8
910111213
CLR
NC
16
15
14
13
12
11
10
9
V
CC
V
CC
6Q
6D
5D
5Q
4D
4Q
CLK
6Q
18
17
16
15
14
6D
5D
NC
5Q
4D
SN54ALS175, SN54AS175B ...J PACKAGE
SN74ALS175, SN74AS175B ...D OR N PACKAGE
SN54ALS175A, SN54AS175B . . . FK PACKAGE
1Q
1D
NC
2D
2Q
(TOP VIEW)
CLR
1
1Q
2
1Q
3
1D
4
2D
5
2Q
6
2Q
7
GND
8
(TOP VIEW)
1Q
3212019
4
5
6
7
8
910111213
CLR
NC
16
15
14
13
12
11
10
9
V
CC
V
CC
4Q
4Q
4D
3D
3Q
3Q
CLK
4Q
18
17
16
15
14
4Q
4D
NC
3D
3Q
NC
CLK
4Q
2Q
GND
NC
CLK
3Q
3Q
GND
NC – No internal connection
description
These positive-edge-triggered flip-flops utilize TTL circuitry to implement D-type flip-flop logic. All have a
direct-clear (CLR
Information at the data (D) inputs meeting the setup-time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock triggering occurs at a particular voltage level and is not directly
related to the transition time of the positive-going pulse. When the clock (CLK) input is at either the high or low
level, the D-input signal has no effect at the output.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
) input. The ’ALS175 and ’AS175B feature complementary outputs from each flip-flop.
Copyright 1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MA Y 1996
description (continued)
These circuits are fully compatible for use with most TTL circuits.
The SN54ALS174, SN54ALS175, SN54AS174, and SN54AS175B are characterized for operation over the full
military temperature range of –55°C to 125°C. The SN74ALS174, SN74ALS175, SN74AS174, and
SN74AS175B are characterized for operation from 0°C to 70°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
CLR CLK D Q Q
L X X L H
H ↑ HHL
H↑LLH
HLXQ
†
’ALS175 and ’AS175B only
OUTPUTS
Q
0
†
0
logic symbols
1
CLR
9
CLK
3
1D
4
2D
6
3D
11
4D
13
5D
14
6D
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
in numbers shown are for the D, J, and N packages.
‡
’ALS174, ’AS174
R
C1
1D
10
12
15
1
CLR
9
CLK
2
1Q
5
2Q
7
3Q
4Q
5Q
6Q
1D
2D
3D
4D
4
5
12
13
’ALS175, ’AS175B
R
C1
1D
10
11
15
14
2
1Q
3
1Q
7
2Q
6
2Q
3Q
3Q
4Q
4Q
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
S
CLK↑
ns
logic diagrams (positive logic)
’ALS174, ’AS174 ’ALS175, ’AS175B
1
CLR
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MA Y 1996
1
CLR
9
CLK
3
1D
To Five Other Channels
Pin numbers shown are for the D, J, and N packages.
1D
C1
R
2
1Q
CLK
1D
9
4
To Three Other Channels
1D
R
2
C1
3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54ALS174, SN54ALS175 –55°C to 125°C. . . . . . . . . . . . . . . .
A
SN74ALS174, SN74ALS175 0°C to 70°C. . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
t
w
su
t
h
T
A
SN54ALS174
SN54ALS175
MIN NOM MAX MIN NOM MAX
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
High-level output current –0.4 –0.4 mA
Low-level output current 4 8 mA
Clock frequency 0 40 0 50 MHz
CLR low 15 10
Pulse duration
etup time before
Hold time, data after CLK↑ 0 0 ns
Operating free-air temperature –55 125 0 70 °C
CLK high
CLK low 12.5 10
Data 15 10
CLR inactive 8 6
12.5 10
SN74ALS174
SN74ALS175
UNIT
ns
1Q
1Q
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
VOLV
4.5 V
V
I
V
V
V
mA
I
V
See Note 1
mA
PARAMETER
UNIT
)
CLR
yQ( )
ns
CLK
y
ns
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MA Y 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ALS174
PARAMETER TEST CONDITIONS
V
IK
V
OH
I
I
I
IH
IL
I
O
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 1: ICC is measured with D inputs and CLR
All others
CLK
‡
’ALS174
’ALS175
VCC = 4.5 V, II = –18 mA –1.5 –1.5 V
VCC = 4.5 V to 5.5 V, IOH = –0.4 mA VCC–2 VCC–2 V
=
CC
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
= 5.5 V,
CC
VCC = 5.5 V, VO = 2.25 V –20 –112 –30 –112 mA
= 5.5 V,
CC
IOL = 4 mA 0.25 0.4 0.25 0.4
IOL = 8 mA 0.35 0.5
= 0.4
I
grounded, and CLK at 4.5 V .
SN54ALS175
MIN TYP†MAX MIN TYP†MAX
–0.1 –0.1
–0.15
11 19 11 19
8 14 9 14
SN74ALS174
SN74ALS175
UNIT
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
FROM
(INPUT) (OUTPUT)
f
max
t
PLH
t
PHL
t
PLH
t
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
TO
Any Q (’ALS175
Any Q
Any Q
(or Q, ’ALS175)
RL = 500 Ω
TA = MIN to MAX
SN54ALS174
SN54ALS175
MIN MAX MIN MAX
40 50 MHz
3 20 5 18
5 30 8 23
3 20 3 15
5 24 5 17
,
§
SN74ALS174
SN74ALS175
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
tw*
Pulse duration
ns
CLK lo
Data
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MA Y 1996
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
: SN54AS174, SN54AS175B –55°C to 125°C. . . . . . . . . . . . . . . .
A
SN74AS174, SN74AS175B 0°C to 70°C. . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions
SN54AS174
SN54AS175B
MIN NOM MAX MIN NOM MAX
V
V
V
I
OH
I
OL
f
clock
tsu*
th* Hold time, data after CLK↑ 1 1 ns
T
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage 2 2 V
IH
Low-level input voltage 0.8 0.8 V
IL
High-level output current –2 –2 mA
Low-level output current 20 20 mA
* Clock frequency 0 100 0 100 MHz
CLR low 5.5 5
*
Setup time before CLK↑
Operating free-air temperature –55 125 0 70 °C
A
CLK high 4 4
w
CLR inactive 6 6
’AS174 6 6
’AS175B 5 5
’AS174 4 4
’AS175B 3 3
SN74AS174
SN74AS175B
UNIT
ns
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
I
V
See Note 2
mA
(
)
(
)
(INPUT)
(OUTPUT)
CLK
Any Q
ns
(
)
(
)
(INPUT)
(OUTPUT)
CLR
A
Q
ns
CLK
A
Q
ns
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MA Y 1996
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54AS174
PARAMETER TEST CONDITIONS
V
IK
V
OH
V
OL
I
I
I
IH
I
IL
‡
I
O
CC
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 2: ICC is measured with D inputs, CLR
’AS174
’AS175B
VCC = 4.5 V, II = –18 mA –1.2 –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2 VCC–2 V
VCC = 4.5 V, IOL = 20 mA 0.35 0.5 0.35 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 20 µA
VCC = 5.5 V, VI = 0.4 V –0.5 –0.5 mA
VCC = 5.5 V, VO = 2.25 V –30 –112 –30 –112 mA
= 5.5 V,
CC
, and CLK grounded.
SN54AS175B
MIN TYP†MAX MIN TYP†MAX
30 45 30 45
22.5 34 22.5 34
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
f
* 100 100 MHz
max
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-STD-883, Class B, these parameters are based on characterization data but are not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
FROM
INPUT
CLR
TO
OUTPUT
Any Q 5 15 5 14 ns
RL = 500 Ω
TA = MIN to MAX
SN54AS174 SN74AS174
MIN MAX MIN MAX
3.5 9.5 3.5 8
4.5 11.5 4.5 10
SN74AS174
SN74AS175B
,
§
UNIT
UNIT
switching characteristics (see Figure 1)
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
PARAMETER
f
* 100 100 MHz
max
t
PLH
t
PHL
t
PLH
t
PHL
* On products compliant to MIL-STD-883, Class B, this parameter is based on characterization data but is not production tested.
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
6
FROM
INPUT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TO
OUTPUT
ny Q or
ny Q or
RL = 500 Ω
TA = MIN to MAX
SN54AS175B SN74AS175B
MIN MAX MIN MAX
4 10 4 9
4.5 15 4.5 13
3 8.5 3 7.5
3 11 3 10
,
§
UNIT
From Output
Under Test
(see Note A)
SN54ALS174, SN54ALS175, SN54AS174, SN54AS175B
SN74ALS174, SN74ALS175, SN74AS174, SN74AS175B
HEX/QUADRUPLE D-TYPE FLIP-FLOPS WITH CLEAR
SDAS207D - APRIL 1982 - REVISED MA Y 1996
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
7 V
V
CC
S1
R
L
Test
Point
C
L
R
L
From Output
Under Test
C
(see Note A)
Test
Point
L
From Output
Under Test
(see Note A)
R1
C
L
RL = R1 = R2
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
t
PZL
t
PZH
VOLTAGE WA VEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
FOR OPEN-COLLECTOR OUTPUTS
t
h
1.3 V1.3 V
1.3 V1.3 V
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Pulse
Low-Level
Pulse
Input
In-Phase
Output
Out-of-Phase
Output
(see Note C)
LOAD CIRCUIT
FOR 3-STATE OUTPUTS
1.3 V 1.3 V
t
w
1.3 V 1.3 V
VOLTAGE WA VEFORMS
PULSE DURATIONS
1.3 V 1.3 V
t
PLH
t
PHL
1.3 V 1.3 V
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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Copyright 1998, Texas Instruments Incorporated
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