Small-Outline (D) Packages, Ceramic Chip
Carriers (FK), and Standard Plastic (N) and
Ceramic (J) 300-mil DIPs
description
These data selectors/multiplexers contain
inverters and drivers to supply full data selection
to the four output gates. A separate strobe (G
input is provided. A 4-bit word is selected from one
of two sources and is routed to the four outputs.
The ′ALS157A and SN74AS157 present true
data. The ′ALS158 and SN74AS158 present
inverted data to minimize propagation delay time.
The SN54ALS157A and SN54ALS158 are
characterized for operation over the full military
temperature range of –55°C to 125°C. The
SN74ALS157A, SN74ALS158, SN74AS157, and
SN74AS158 are characterized for operation from
0°C to 70°C.
SN54ALS157A, SN54ALS158 ...J PACKAGE
SN74AS157, SN74AS158 ...D OR N PACKAGE
)
SN54ALS157A, SN54ALS158 . . . FK PACKAGE
SN74ALS157A, SN74ALS158,
(TOP VIEW)
NC
16
15
14
13
12
11
10
V
9
CC
V
G
4A
4B
4Y
3A
3B
3Y
18
17
16
15
14
1B
1Y
NC
2A
2B
1
A/B
2
1A
3
1B
4
1Y
5
2A
6
2B
7
2Y
GND
8
(TOP VIEW)
1A
A/B
3212019
4
5
6
7
8
910111213
CC
4A
4B
NC
4Y
3A
2Y
NC – No internal connection
FUNCTION TABLE
INPUTS
DATA
AB
HXXXLH
LLLXLH
LLHXHL
LHXLLH
LHXHHL
OUTPUT Y
′ALS157A′ALS158
SN74AS157 SN74AS158
GND
NC
3Y
3BG
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1994, Texas Instruments Incorporated
1
SN54ALS157A, SN54ALS158
SN74ALS157A, SN74ALS158, SN74AS157, SN74AS158
QUAD 1-OF-2 DATA SELECTORS/MULTIPLEXERS
SDAS081C – APRIL 1982 – REVISED DECEMBER 1994
logic symbols
15
G
1
A/B
2
1A
3
1B
5
2A
6
2B
11
3A
10
3B
14
4A
13
4B
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
†
′ALS157A, SN74AS157′ALS158, SN74AS158
A/B
1A
1B
2A
2B
3A
3B
4A
4B
15
G
1
2
3
5
6
11
10
14
13
EN
G1
1
1
MUX
12
4
1Y
7
2Y
9
3Y
4Y
EN
G1
1
1
MUX
12
4
1Y
7
2Y
9
3Y
4Y
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagrams (positive logic)
′ALS157A′ALS158
1A
1B
2
3
SN54ALS157A, SN54ALS158
SN74ALS157A, SN74ALS158, SN74AS157, SN74AS158
QUAD 1-OF-2 DATA SELECTORS/MULTIPLEXERS
SDAS081C – APRIL 1982 – REVISED DECEMBER 1994
2
1A
4
1Y
1B
3
4
1Y
5
2A
7
12
2Y
9
3Y
4Y
4
1Y
6
2B
11
3A
10
3B
14
4A
13
4B
15
G
1
A
/B
SN74AS157SN74AS158
1A
1B
2
3
5
2A
7
12
2Y
9
3Y
4Y
4
1Y
6
2B
11
3A
10
3B
14
4A
13
4B
15
G
1
A
/B
2
1A
3
1B
5
2A
6
2B
11
3A
10
3B
14
4A
13
4B
15
G
1
A
/B
Pin numbers shown are for the D, J, and N packages.
12
5
2A
7
2Y
9
3Y
4Y
6
2B
11
3A
10
3B
14
4A
13
4B
15
G
1
A
/B
12
7
2Y
9
3Y
4Y
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN54ALS157A, SN54ALS158
VOLV
V
V
I
V
See Note 1
mA
SN74ALS157A, SN74ALS158, SN74AS157, SN74AS158
QUAD 1-OF-2 DATA SELECTORS/MULTIPLEXERS
SDAS081C – APRIL 1982 – REVISED DECEMBER 1994
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
Operating free-air temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
FROM
INPUT
TO
OUTPUT
switching characteristics (see Figure 1)
PARAMETER
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
PHL
FROM
INPUT
TO
OUTPUT
RL = 500 Ω
TA = MIN to MAX
VCC = 4.5 V to 5.5 V,
CL = 50 pF,
RL = 500 Ω
TA = MIN to MAX
,
SN74AS157
MINMAX
16
15.5
211
210
210.5
27.5
,
SN74AS158
MINMAX
15
14.5
29.5
210.5
26.5
210
†
UNIT
†
UNIT
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN54ALS157A, SN54ALS158
SN74ALS157A, SN74ALS158, SN74AS157, SN74AS158
QUAD 1-OF-2 DATA SELECTORS/MULTIPLEXERS
SDAS081C – APRIL 1982 – REVISED DECEMBER 1994
PARAMETER MEASUREMENT INFORMATION
SERIES 54ALS/74ALS AND 54AS/74AS DEVICES
V
CC
R
L
From Output
Under Test
(see Note A)
C
L
Test
Point
R
L
From Output
Under Test
C
(see Note A)
Test
Point
L
From Output
Under Test
(see Note A)
7 V
RL = R1 = R2
S1
R1
C
L
Test
Point
R2
LOAD CIRCUIT FOR
BI-STATE
TOTEM-POLE OUTPUTS
Timing
Input
t
su
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
Control
(low-level
enabling)
Waveform 1
S1 Closed
(see Note B)
Waveform 2
S1 Open
(see Note B)
t
PZL
t
PZH
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
1.3 V
t
PHZ
1.3 V
1.3 V
t
h
1.3 V1.3 V
1.3 V1.3 V
FOR OPEN-COLLECTOR OUTPUTS
t
PLZ
LOAD CIRCUIT
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
[
3.5 V
V
OL
0.3 V
V
OH
0.3 V
[
0 V
High-Level
Pulse
Low-Level
Pulse
In-Phase
Out-of-Phase
(see Note C)
FOR 3-STATE OUTPUTS
1.3 V1.3 V
1.3 V1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
Input
Output
Output
t
PLH
t
PHL
1.3 V1.3 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT
t
w
1.3 V1.3 V
1.3 V1.3 V
t
PHL
t
PLH
3.5 V
0.3 V
3.5 V
0.3 V
3.5 V
0.3 V
V
V
V
V
OH
OL
OH
OL
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. When measuring propagation delay items of 3-state outputs, switch S1 is open.
D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%.
E. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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