Texas Instruments SN74ALVTH32374KR Datasheet

SN54ALVTH32374, SN74ALVTH32374

2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCES280 – SEPTEMBER 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

State-of-the-Art Advanced BiCMOS
Technology (ABT)

Widebus

 Design for

2.5-V and 3.3-V Operation and Low Static
Power Dissipation

D

Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to

3.6-V V

CC

)

D

T ypical V

OLP

(Output Ground Bounce)

< 0.8 V at VCC = 3.3 V, TA = 25°C

D

High Drive (–24/24 mA at 2.5-V V

CC

and

–32/64 mA at 3.3-V VCC)

D

I

off

and Power-Up 3-State Support Hot

Insertion

D

Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating

NOTE: For tape and reel order entry:

The GKER package is abbreviated to KR.

D

Auto3-State Eliminates Bus Current
Loading When Output Exceeds VCC + 0.5 V

D

Flow-Through Architecture Facilitates
Printed Circuit Board Layout

D

Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise

D

ESD Protection Exceeds JESD-22
– 2000-V Human-Body Model
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)

(A114-A)

D

Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II

D

Packaged in Plastic Fine-Pitch Ball Grid
Array Package

description

The ’ALVTH32374 devices are 32-bit edge-triggered D-type flip-flops with 3-state outputs designed for 2.5-V
or 3.3-V) V

CC

operation, but with the capability to provide a TTL interface to a 5-V system environment. These
devices are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and
working registers.

These devices can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive
transition of the clock (CLK), the Q outputs of the flip-flops take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE

) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly . The high-impedance state and increased drive provide the capability to drive bus lines
without interface or pullup components.

OE

does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.
When VCC is between 0 and 1.2 V , the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 1.2 V, OE should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.

These devices are fully specified for hot-insertion applications using I

off

and power-up 3-state. The I

off

circuitry
disables the outputs, preventing damaging current backflow through the device when they are powered down.
The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH32374 is characterized for operation over the full military temperature range of –55°C to

125°C. The SN74ALVTH32374 is characterized for operation from –40°C to 85°C.

Copyright  1999, Texas Instruments Incorporated

UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus is a trademark of Texas Instruments Incorporated.

SN54ALVTH32374, SN74ALVTH32374

2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCES280 – SEPTEMBER 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

OE

CLK D

Q

L ↑ H H
L ↑ LL
L H or L X Q

0

H X X Z

terminal assignments

1 2 3 4 5 6

A 1Q2 1Q1 1OE 1CLK 1D1 1D2
B 1Q4 1Q3 GND GND 1D3 1D4
C 1Q6 1Q5 1V

CC

1V

CC

1D5 1D6

D 1Q8 1Q7 GND GND 1D7 1D8
E 2Q2 2Q1 GND GND 2D1 2D2
F 2Q4 2Q3 1V

CC

1V

CC

2D3 2D4

G 2Q6 2Q5 GND GND 2D5 2D6
H 2Q7 2Q8 2OE 2CLK 2D8 2D7
J 3Q2 3Q1 3OE 3CLK 3D1 3D2
K 3Q4 3Q3 GND GND 3D3 3D4
L 3Q6 3Q5 2V

CC

2V

CC

3D5 3D6

M 3Q8 3Q7 GND GND 3D7 3D8
N 4Q2 4Q1 GND GND 4D1 4D2
P 4Q4 4Q3 2V

CC

2V

CC

4D3 4D4

R 4Q6 4Q5 GND GND 4D5 4D6
T 4Q7 4Q8 4OE 4CLK 4D8 4D7

GKE PACKAGE

(TOP VIEW)

123456

A

B
C
D

E

F
G
H

J

K

L
M
N

P

R

T

SN54ALVTH32374, SN74ALVTH32374

2.5-V/3.3-V 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS

SCES280 – SEPTEMBER 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1OE

1CLK

1D1

To Seven Other Channels

1Q1

C1
1D

A3

A4

A5

A2

2OE

2CLK

2D1

To Seven Other Channels

2Q1

C1
1D

H3

H4

E5

E2

3OE

3CLK

3D1

To Seven Other Channels

3Q1

C1
1D

J3

J4

J5

J2

4OE

4CLK

4D1

To Seven Other Channels

4Q1

C1
1D

T3

T4

N5

N2

NOTE A: 1VCC is associated with these channels.

NOTE B: 2VCC is associated with these channels.

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high-impedance or power-off state, V

O

(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state, VO (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . .

Output current in the low state, I

O

: SN54ALVTH32374 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALVTH32374 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output current in the high state, IO: SN54ALVTH32374 –48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

SN74ALVTH32374 –64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(V

I

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(V

O

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 2) 40°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51.