Datasheet SN74ALVTH16601DL, SN74ALVTH16601DLR, SN74ALVTH16601GR, SN74ALVTH16601VR Datasheet (Texas Instruments)
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D
State-of-the-Art Advanced BiCMOS
Technology (ABT)
Widebus
Design for
2.5-V and 3.3-V Operation and Low
Static-Power Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
CC
)
D
T ypical V
OLP
(Output Ground Bounce)
<0.8 V at V
CC
= 3.3 V, TA = 25°C
D
High-Drive (–24/24 mA at 2.5-V and
–32/64 mA at 3.3-V V
CC
)
D
I
off
and Power-Up 3-State Support Hot
Insertion
D
Use Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
CC
+ 0.5 V
D
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR and
the DGVR package is abbreviated to VR.
description
The ’AL VTH16601 devices are 18-bit universal bus transceivers designed for 2.5-V or 3.3-V VCC operation, but
with the capability to provide a TTL interface to a 5-V system environment.
The devices combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked
modes.
Copyright 1999, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UBT and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
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5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A1 1
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
CLKENAB
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B1 1
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
CLKENBA
SN54ALVTH16601. . . WD PACKAGE
SN74ALVTH16601. . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB
and
CLKENBA
) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low , the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. Output enable OEAB
is active low. When OEAB is
low, the outputs are active. When OEAB
is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA
, LEBA, CLKBA, and CLKENBA.
This device is fully specified for hot-insertion applications using I
off
and power-up 3-state. The I
off
circuitry
disables the outputs, preventing damaging current backflow through the device when it is powered down. The
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,
which prevents driver conflict.
When V
CC
is between 0 and 1.2 V , the device is in the high-impedance state during power up or power down.
However, to ensure the high-impedance state above 1.2 V, OE
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54ALVTH16601 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH16601 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
†
INPUTS
OUTPUT
CLKENAB OEAB LEAB
CLKAB A
B
X H X X X Z
X LH XL L
X LH XH H
H LL XXB
0
‡
H LL XXB
0
‡
L LL ↑LL
L LL ↑HH
L LLL or H X B
0
‡
†
A-to-B data flow is shown: B-to-A flow is similar but uses OEBA,
LEBA, CLKBA, and CLKENBA
.
‡
Output level before the indicated steady-state input conditions were
established
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
CE
1D
C1
CLK
CE
1D
C1
CLK
B1
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
3
54
To 17 Other Channels
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or power-off state, V
O
(see Note 1) –0.5 V to 7 V. . . . . . . . .
Output current in the low state, I
O
: SN54ALVTH16601 96 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH16601 128 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current in the high state, I
O
: SN54ALVTH16601 –48 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SN74ALVTH16601 –64 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 2): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH16601 SN74ALVTH16601
MIN TYP MAX MIN TYP MAX
UNIT
V
CC
Supply voltage 2.3 2.7 2.3 2.7 V
V
IH
High-level input voltage 1.7 1.7 V
V
IL
Low-level input voltage 0.7 0.7 V
V
I
Input voltage 0 V
CC
5.5 0 V
CC
5.5 V
I
OH
High-level output current –6 –8 mA
Low-level output current 6 8
I
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 18 24
mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)
SN54ALVTH16601 SN74ALVTH16601
MIN TYP MAX MIN TYP MAX
UNIT
V
CC
Supply voltage 3 3.6 3 3.6 V
V
IH
High-level input voltage 2 2 V
V
IL
Low-level input voltage 0.8 0.8 V
V
I
Input voltage 0 V
CC
5.5 0 V
CC
5.5 V
I
OH
High-level output current –24 –32 mA
Low-level output current 24 32
I
OL
Low-level output current; current duty cycle ≤ 50%; f ≥ 1 kHz 48 64
mA
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
CC
Power-up ramp rate 200 200 µs/V
T
A
Operating free-air temperature –55 125 –40 85 °C
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= 2.5 V ± 0.2 V (unless otherwise noted)
SN54ALVTH16601 SN74ALVTH16601
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 2.3 V, II = –18 mA –1.2 –1.2 V
VCC = 2.3 V to 2.7 V, IOH = –100 µA VCC–0.2 VCC–0.2
V
OH
IOH = –6 mA 1.8
V
V
CC
= 2.3
V
IOH = –8 mA 1.8
VCC = 2.3 V to 2.7 V, IOL = 100 µA 0.2 0.2
IOL = 6 mA 0.4
V
OL
IOL = 8 mA 0.4
V
V
CC
= 2.3
V
IOL = 18 mA 0.5
IOL = 24 mA 0.5
V
RST
‡
VCC = 2.7 V
IO = 1 mA,
VI = VCC or GND
0.55 0.55 V
p
VCC = 2.7 V, VI = VCC or GND ±1 ±1
Control inputs
VCC = 0 or 2.7 V, VI = 5.5 V 10 10
I
I
VI = 5.5 V 10 10
µA
A or B ports VCC = 2.7 V
VI = V
CC
1 1
VI = 0 –5 –5
I
off
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
I
BHL
§
VCC = 2.3 V, VI = 0.7 V 115 115 µA
I
BHH
¶
VCC = 2.3 V, VI = 1.7 V –10 –10 µA
I
BHLO
#
VCC = 2.7 V, VI = 0 to V
CC
300 300 µA
I
BHHO
||
VCC = 2.7 V, VI = 0 to V
CC
–300 –300 µA
I
EX
k
VCC = 2.3 V, VO = 5.5 V 125 125 µA
I
OZ(PU/PD)
h
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE
= don’t care
±100 ±100 µA
=
Outputs high 0.04 0.1 0.04 0.1
I
CC
V
CC
= 2.7 V,
IO = 0,
Outputs low 2.5 4.5 2.5 4.5
mA
VI = VCC or GND
Outputs disabled 0.04 0.1 0.04 0.1
C
i
VCC = 2.5 V, VI = 2.5 V or 0 3 3 pF
C
io
VCC = 2.5 V, VO = 2.5 V or 0 7 7 pF
†
All typical values are at VCC = 2.5 V, TA = 25°C.
‡
Data must not be loaded into the flip-flops/latches after applying power.
§
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. I
BHL
should be measured after lowering VIN to GND and
then raising it to VIL max.
¶
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. I
BHH
should be measured after raising VIN to VCC and
then lowering it to VIH min.
#
An external driver must source at least I
BHLO
to switch this node from low to high.
||
An external driver must sink at least I
BHHO
to switch this node from high to low.
k
Current into an output in the high state when VO > V
CC
h
High-impedance state during power up or power down
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted)
SN54ALVTH16601 SN74ALVTH16601
PARAMETER
TEST CONDITIONS
MIN TYP†MAX MIN TYP†MAX
UNIT
V
IK
VCC = 3 V, II = –18 mA –1.2 –1.2 V
VCC = 3 V to 3.6 V, IOH = –100 µA VCC–0.2 VCC–0.2
V
OH
IOH = –24 mA 2
V
V
CC
= 3
V
IOH = –32 mA 2
VCC = 3 V to 3.6 V, IOL = 100 µA 0.2 0.2
IOL = 16 mA 0.4
IOL = 24 mA 0.5
V
OL
VCC = 3 V
IOL = 32 mA 0.5
V
IOL = 48 mA 0.55
IOL = 64 mA 0.55
V
RST
‡
VCC = 3.6 V
IO = 1 mA,
VI = VCC or GND
0.55 0.55 V
p
VCC = 3.6 V, VI = VCC or GND ±1 ±1
Control inputs
VCC = 0 or 3.6 V, VI = 5.5 V 10 10
I
I
VI = 5.5 V 10 10
µA
A or B ports VCC = 3.6 V
VI = V
CC
1 1
VI = 0 –5 –5
I
off
VCC = 0, VI or VO = 0 to 4.5 V ±100 µA
I
BHL
§
VCC = 3 V, VI = 0.8 V 75 75 µA
I
BHH
¶
VCC = 3 V, VI = 2 V –75 –75 µA
I
BHLO
#
VCC = 3.6 V, VI = 0 to V
CC
500 500 µA
I
BHHO
||
VCC = 3.6 V, VI = 0 to V
CC
–500 –500 µA
I
EX
k
VCC = 3 V, VO = 5.5 V 125 125 µA
I
OZ(PU/PD)
h
VCC ≤ 1.2 V, VO = 0.5 V to VCC,
VI = GND or VCC, OE
= don’t care
±100 ±100 µA
=
Outputs high 0.06 0.1 0.06 0.1
I
CC
V
CC
= 3.6 V,
IO = 0,
Outputs low 3.5 5 3.5 5
mA
VI = VCC or GND
Outputs disabled 0.06 0.1 0.06 0.1
∆ICC◊
VCC = 3 V to 3.6 V, One input at VCC – 0.6 V,
Other inputs at VCC or GND
0.4 0.4 mA
C
i
VCC = 3.3 V, VI = 3.3 V or 0 3 3 pF
C
io
VCC = 3.3 V, VO = 3.3 V or 0 7 7 pF
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
Data must not be loaded into the flip-flops/latches after applying power.
§
The bus-hold circuit can sink at least the minimum low sustaining current at VIL max. I
BHL
should be measured after lowering VIN to GND and
then raising it to VIL max.
¶
The bus-hold circuit can source at least the minimum high sustaining current at VIH min. I
BHH
should be measured after raising VIN to VCC and
then lowering it to VIH min.
#
An external driver must source at least I
BHLO
to switch this node from low to high.
||
An external driver must sink at least I
BHHO
to switch this node from high to low.
k
Current into an output in the high state when VO > V
CC
h
High-impedance state during power up or power down
◊ This is the increase in supply current for each input that is at the specified TTL voltage level rather than VCC or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, VCC = 2.5 V ± 0.2 V
(unless otherwise noted) (see Figure 1)
SN54ALVTH16601 SN74ALVTH16601
MIN MAX MIN MAX
UNIT
f
clock
Clock frequency 150 150 MHz
LE high 1.8 1.8
twPul
se duration
CLK high or low
2.3 2.3
ns
Data high 4 4
A
or B before
CLK↑
Data low 5.2 5.2
p
CLK high
0.7 0.7
tsuSetup time
A
or B before
LE↓
CLK low
0.9 0.9
ns
Data high 1.7 1.7
CLKEN bef
ore
CLK↑
Data low 2.3 2.3
Data high 0.5 0.5
A
or B after
CLK↑
Data low
0.5 0.5
CLK high 2.3 2.3
thHold time
A or B after LE↓
CLK low
2.4 2.4
ns
Data high 0.5 0.5
CLKEN aft
er
CLK↑
Data low 0.5 0.5
timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V
(unless otherwise noted) (see Figure 2)
SN54ALVTH16601 SN74ALVTH16601
MIN MAX MIN MAX
UNIT
f
clock
Clock frequency 150 150 MHz
LE high 1.8 1.8
twPul
se duration
CLK high or low
2.3 2.3
ns
Data high 2.4 2.4
A
or B before
CLK↑
Data low 3.8 3.8
p
CLK high
1 1
tsuSetup time
A
or B before
LE↓
CLK low
0.6 0.6
ns
Data high 1.4 1.4
CLKEN bef
ore
CLK↑
Data low 1.9 1.9
Data high 0.5 0.5
A
or B after
CLK↑
Data low
0.5 0.5
CLK high 2 2
thHold time
A or B after LE↓
CLK low
2.3 2.3
ns
Data high 0.6 0.6
CLKEN aft
er
CLK↑
Data low 0.5 0.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended operating free-air temperature range, CL = 30 pF,
V
CC
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
FROM TO
SN54ALVTH16601 SN74ALVTH16601
PARAMETER
(INPUT) (OUTPUT)
MIN MAX MIN MAX
UNIT
f
max
150 150 MHz
t
PLH
1.1 4.1 1.1 4.1
t
PHL
B
or
A
A or B
1.6 4.8 1.6 4.8
ns
t
PLH
2.1 5 2.1 5
t
PHL
LEBA
or
LEAB
A or B
2.4 5.4 2.4 5.4
ns
t
PLH
2 5 2 5
t
PHL
CLKBA
or
CLKAB
A or B
2.5 5.9 2.5 5.9
ns
t
PZH
1.2 4.8 1.2 4.8
t
PZL
OEBA
or
OEAB
A or B
1 4.6 1 4.6
ns
t
PHZ
1.2 5.2 1.2 5.2
t
PLZ
OEBA or OEAB
A or B
1 3.9 1 3.9
ns
switching characteristics over recommended operating free-air temperature range, CL = 50 pF,
V
CC
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 2)
FROM TO
SN54ALVTH16601 SN74ALVTH16601
PARAMETER
(INPUT) (OUTPUT)
MIN MAX MIN MAX
UNIT
f
max
150 150 MHz
t
PLH
1.4 3.9 1.4 3.9
t
PHL
B
or
A
A or B
1.1 3.9 1.1 3.9
ns
t
PLH
2 4.6 2 4.6
t
PHL
LEBA
or
LEAB
A or B
2.1 4.6 2.1 4.6
ns
t
PLH
1.9 4.5 1.9 4.5
t
PHL
CLKBA
or
CLKAB
A or B
2.2 4.6 2.2 4.6
ns
t
PZH
1 4.2 1 4.2
t
PZL
OEBA
or
OEAB
A or B
1 4.4 1 4.4
ns
t
PHZ
1.8 5.3 1.8 5.3
t
PLZ
OEBA or OEAB
A or B
1.7 4.6 1.7 4.6
ns
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
CC
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
V
CC
0 V
0 V
t
w
V
CC
V
CC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
CC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
0 V
V
CC
VCC/2
t
PHL
VCC/2 VCC/2
V
CC
0 V
V
OH
V
OL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
t
PLH
2 × V
CC
V
CC
Figure 1. Load Circuit and Voltage Waveforms
SN54ALVTH16601, SN74ALVTH16601
2.5-V/3.3-V 18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES143A – SEPTEMBER 1998 – REVISED JUL Y 1999
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
V
CC
= 3.3 V ± 0.3 V
V
OH
V
OL
t
h
t
su
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1
Open
GND
500 Ω
500 Ω
t
PLH
t
PHL
Output Control
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
t
PZH
t
PLZ
t
PHZ
3 V
0 V
V
OH
V
OL
0 V
VOL + 0.3 V
VOH – 0.3 V
≈ 0 V
3 V
0 V
0 V
t
w
Input
3 V
3 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
Timing
Input
Data
Input
Output
Input
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform22 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
6 V
1.5 V
1.5 V 1.5 V
1.5 V 1.5 V
0 V
3 V
1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V 1.5 V
Figure 2. Load Circuit and Voltage Waveforms
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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