Texas Instruments SN74ALVTH162244DL, SN74ALVTH162244GR, SN74ALVTH162244LR, SN74ALVTH162244VR Datasheet
SN54ALVTH162244, SN74ALVTH162244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES074E – JUNE 1996 - REVISED JANUARY 1999
D
State-of-the-Art Advanced BiCMOS
Technology (ABT)
Widebus
Design for
2.5-V and 3.3-V Operation and Low Static
Power Dissipation
D
Support Mixed-Mode Signal Operation (5-V
Input and Output Voltages With 2.3-V to
3.6-V V
D
Typical V
< 0.8 V at V
D
Power Off Disables Outputs, Permitting
)
CC
(Output Ground Bounce)
OLP
= 3.3 V, TA = 25°C
CC
Live Insertion
D
High-Impedance State During Power Up
and Power Down Prevents Driver Conflict
D
Uses Bus Hold on Data Inputs in Place of
External Pullup/Pulldown Resistors to
Prevent the Bus From Floating
D
Output Ports Have Equivalent 30-Ω Series
Resistors, So No External Resistors Are
Required
D
Auto3-State Eliminates Bus Current
Loading When Output Exceeds V
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model; and Exceeds 1000 V
Using Charged-Device Model, Robotic
Method
D
Flow-Through Architecture Facilitates
Printed Circuit Board Layout
D
Distributed VCC and GND Pin Configuration
Minimizes High-Speed Switching Noise
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), Thin Very
Small-Outline (DGV) Packages, and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
NOTE: For order entry:
The DGG package is abbreviated to G, and
the DGV package is abbreviated to V.
+ 0.5 V
CC
SN54ALVTH162244. . . WD PACKAGE
SN74ALVTH162244. . . DGG, DGV, OR DL PACKAGE
1OE
1Y1
1Y2
GND
1Y3
1Y4
V
CC
2Y1
2Y2
GND
2Y3
2Y4
3Y1
3Y2
GND
3Y3
3Y4
V
CC
4Y1
4Y2
GND
4Y3
4Y4
4OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE
1A1
1A2
GND
1A3
1A4
V
CC
2A1
2A2
GND
2A3
2A4
3A1
3A2
GND
3A3
3A4
V
CC
4A1
4A2
GND
4A3
4A4
3OE
description
The ’ALVTH162244 devices are 16-bit buffers/line drivers designed for low-voltage 2.5-V or 3.3-V V
operation, but with the capability to provide a TTL interface to a 5-V system environment.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
CC
1
SN54ALVTH162244, SN74ALVTH162244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES074E – JUNE 1996 - REVISED JANUARY 1999
description (continued)
These devices can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. These devices provide
true outputs and symmetrical active-low output-enable (OE
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
) inputs.
When V
However, to ensure the high-impedance state above 1.2 V, OE
is between 0 and 1.2 V , the device is in the high-impedance state during power up or power down.
CC
should be tied to VCC through a pullup resistor;
the minimum value of the resistor is determined by the current-sinking capability of the driver.
All outputs are designed to sink up to 12 mA and include equivalent 30-Ω resistors to reduce overshoot and
undershoot.
The SN54ALVTH162244 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ALVTH162244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE
L H H
L LL
HXZ
OUTPUT
A
Y
logic diagram (positive logic)
1OE
1A1
1
47
2
1Y1
3OE
3A1
25
36
13
3Y1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
46
44
43
48
41
40
38
37
11
12
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2
2Y3
2Y4
3A2
3A3
3A4
4OE
4A1
4A2
4A3
4A4
35
33
32
24
30
29
27
26
14
16
17
19
20
22
23
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
UNIT
UNIT
SN54ALVTH162244, SN74ALVTH162244
2.5-V/3.3-V 16-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCES074E – JUNE 1996 - REVISED JANUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Voltage range applied to any output in
or power-off state, V
Voltage range applied to any output in the high state, V
Output current in the low state, I
Output current in the high state, I
Input clamp current, I
Output clamp current, I
Package thermal impedance, θ
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
the high-impedance
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
–30 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 2): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
IK
(V
OK
I
(see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . .
O
†
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions, VCC = 2.5 V ± 0.2 V (see Note 3)
SN54ALVTH162244 SN74ALVTH162244
MIN TYP MAX MIN TYP MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 2.3 2.7 2.3 2.7 V
High-level input voltage 1.7 1.7 V
Low-level input voltage 0.7 0.7 V
Input voltage 0 V
High-level output current –6 –8 mA
Low-level output current 8 12 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
CC
5.5 0 V
CC
5.5 V
recommended operating conditions, VCC = 3.3 V ± 0.3 V (see Note 3)
SN54ALVTH162244 SN74ALVTH162244
MIN TYP MAX MIN TYP MAX
V
CC
V
IH
V
IL
V
I
I
OH
I
OL
∆t/∆v Input transition rise or fall rate Outputs enabled 10 10 ns/V
∆t/∆V
T
A
NOTE 3: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
Supply voltage 3 3.6 3 3.6 V
High-level input voltage 2 2 V
Low-level input voltage 0.8 0.8 V
Input voltage 0 V
High-level output current –8 –12 mA
Low-level output current 8 12 mA
Power-up ramp rate 200 200 µs/V
CC
Operating free-air temperature –55 125 –40 85 °C
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CC
5.5 0 V
CC
5.5 V
3
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