Texas Instruments SN74ALVCHR16601GR, SN74ALVCHR16601LR, SN74ALVCHR16601VR Datasheet

SN74ALVCHR16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES123G – SEPTEMBER 1997 – REVISED JUNE 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode

D

Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages

NOTE: For tape and reel order entry:

The DGGR package is abbreviated to GR,
the DGVR package is abbreviated to VR, and
the DLR package is abbreviated to LR.

description

This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V VCC operation.

The SN74ALVCHR16601 combines D-type latches and D-type flip-flops to allow data flow in transparent,
latched, clocked, and clock-enabled modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and
CLKENBA) inputs. For A-to-B data flow , the device operates in the transparent mode when LEAB is high. When
LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low , the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB

is low, the outputs are active. When

OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA, LEBA, CLKBA, and CLKENBA.
The outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Copyright  1999, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, EPIC, and UBT are trademarks of Texas Instruments Incorporated.

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

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OEAB

LEAB

A1

GND

A2
A3

V

CC

A4
A5
A6

GND

A7
A8

A9
A10
A11
A12

GND

A13
A14
A15

V

CC

A16
A17

GND

A18

OEBA

LEBA

CLKENAB
CLKAB
B1
GND
B2
B3
V

CC

B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V

CC

B16
B17
GND
B18
CLKBA
CLKENBA

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN74ALVCHR16601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES123G – SEPTEMBER 1997 – REVISED JUNE 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCHR16601 is characterized for operation from –40°C to 85°C.

FUNCTION TABLE

†

INPUTS

OUTPUT

CLKENAB OEAB

LEAB

CLKAB

A

B

X H X X X Z
X LH XL L
X LH XH H
H LL XXB

0

‡

L LL ↑ LL
L LL ↑ HH
L L L L or H X B

0

‡

†

A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA

,

LEBA, CLKBA, and CLKENBA

.

‡

Output level before the indicated steady-state input conditions were
established

logic diagram (positive logic)

CE

1D
C1

CLK

CE
1D
C1

CLK

B1

OEAB

CLKENAB

CLKAB

LEAB

LEBA

CLKBA

CLKENBA

OEBA

A1

1

56

55

2

28

30

29

27

3

54

To 17 Other Channels

SN74ALVCHR16601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES123G – SEPTEMBER 1997 – REVISED JUNE 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O ports (see Notes 1 and 2) –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each V

CC

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN MAX UNIT

V

CC

Supply voltage 1.65 3.6 V

VCC = 1.65 V to 1.95 V 0.65 × V

CC

V

IH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V

CC

V

IL

Low-level input voltage

VCC = 2.3 V to 2.7 V

0.7

V
VCC = 2.7 V to 3.6 V 0.8

V

I

Input voltage 0 V

CC

V

V

O

Output voltage 0 V

CC

V
VCC = 1.65 V –2

p

VCC = 2.3 V –6

IOHHigh-level output current

VCC = 2.7 V –8

mA

VCC = 3 V –12
VCC = 1.65 V 2

p

VCC = 2.3 V 6

IOLLow-level output current

VCC = 2.7 V 8

mA

VCC = 3 V 12

∆t/∆v Input transition rise or fall rate 10 ns/V
T

A

Operating free-air temperature –40 85 °C

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.