Texas Instruments SN74ALVCHR16269AGR, SN74ALVCHR16269AL, SN74ALVCHR16269ALR, SN74ALVCHR16269AVR Datasheet
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
All Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
NOTE: For order entry:
The DGG package is abbreviated to G,
the DGV package is abbreviated to V , and
the DL package is abbreviated to L.
For tape and reel:
The DGGR package is abbreviated to GR,
the DGVR package is abbreviated to VR, and
the DLR package is abbreviated to LR.
description
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V
The SN74AL VCHR16269A is used in applications
in which two ports must be multiplexed onto, or
demultiplexed from, a single port. It is particularly
suitable as an interface between synchronous
DRAMs and high-speed microprocessors.
operation.
CC
DGG, DGV, OR DL PACKAGE
OEB1
(TOP VIEW)
OEA
1
2
2B3
3
GND
GND
GND
GND
NC – No internal connection
2B2
2B1
V
CC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1 1
A12
V
CC
1B1
1B2
1B3
NC
SEL
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEB2
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B1 1
2B12
1B12
1B1 1
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the
appropriate clock-enable (CLKENA
) inputs are low. Proper control of these inputs allows two sequential 12-bit
words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage
register is provided. The select (SEL
) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus.
The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled
by the active-low output enables (OEA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
, OEB1, and OEB2).
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
description (continued)
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible and OE
determined by the current-sinking capability of the driver. Due to OE
state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
All outputs are designed to sink up to 12 mA, and include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
The SN74ALVCHR16269A is characterized for operation from –40°C to 85°C.
should be tied to VCC through a pullup resistor; the minimum value of the resistor is
being routed through a register, the active
Function Tables
OUTPUT ENABLE
INPUTS
CLK OEA OEB A 1B, 2B
↑ H H Z Z
↑ HL ZActive
↑ L H Active Z
↑ L L Active Active
OUTPUTS
A-TO-B STORAGE
(OEB
= L)
INPUTS
CLKENA1 CLKENA2 CLK A 1B 2B
L H ↑ L L 2B
L H ↑ HH2B
L L ↑ LLL
L L ↑HHH
H L ↑L1B
H L ↑ H1B
H H X X1B
†
Output level before the indicated steady-state input
conditions were established
B-TO-A STORAGE
(OEA
= L)
INPUTS
CLK SEL 1B 2B
X H X X A
X LXX A
↑HLX L
↑HHX H
↑LXL L
↑LXH H
†
Output level before the indicated steady-state
input conditions were established
OUTPUTS
†
0
†
0
†
0
OUTPUT
A
†
0
†
0
2B
†
0
†
0
L
H
†
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
29
CLK
2
OEB1
56
OEB2
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
C1
1D
C1
1D
CLKENA1
CLKENA2
SEL
OEA
A1
30
55
28
1
8
C1
1D
C1
1D
C1
1D
1 of 12 Channels
G1
1
1
CE
C1
1D
23
1B1
6
2B1
CE
C1
1D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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