Datasheet SN74ALVCHR16269AGR, SN74ALVCHR16269AL, SN74ALVCHR16269ALR, SN74ALVCHR16269AVR Datasheet (Texas Instruments)
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
All Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Thin
Shrink Small-Outline (DGG), Thin Very
Small-Outline (DGV), and 300-mil Shrink
Small-Outline (DL) Packages
NOTE: For order entry:
The DGG package is abbreviated to G,
the DGV package is abbreviated to V , and
the DL package is abbreviated to L.
For tape and reel:
The DGGR package is abbreviated to GR,
the DGVR package is abbreviated to VR, and
the DLR package is abbreviated to LR.
description
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V
The SN74AL VCHR16269A is used in applications
in which two ports must be multiplexed onto, or
demultiplexed from, a single port. It is particularly
suitable as an interface between synchronous
DRAMs and high-speed microprocessors.
operation.
CC
DGG, DGV, OR DL PACKAGE
OEB1
(TOP VIEW)
OEA
1
2
2B3
3
GND
GND
GND
GND
NC – No internal connection
2B2
2B1
V
CC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1 1
A12
V
CC
1B1
1B2
1B3
NC
SEL
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEB2
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B1 1
2B12
1B12
1B1 1
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
Data is stored in the internal B-port registers on the low-to-high transition of the clock (CLK) input when the
appropriate clock-enable (CLKENA
) inputs are low. Proper control of these inputs allows two sequential 12-bit
words to be presented as a 24-bit word on the B port. For data transfer in the B-to-A direction, a single storage
register is provided. The select (SEL
) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, thus extending the period during which the data is valid on the bus.
The control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled
by the active-low output enables (OEA
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
, OEB1, and OEB2).
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
description (continued)
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible and OE
determined by the current-sinking capability of the driver. Due to OE
state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
All outputs are designed to sink up to 12 mA, and include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
The SN74ALVCHR16269A is characterized for operation from –40°C to 85°C.
should be tied to VCC through a pullup resistor; the minimum value of the resistor is
being routed through a register, the active
Function Tables
OUTPUT ENABLE
INPUTS
CLK OEA OEB A 1B, 2B
↑ H H Z Z
↑ HL ZActive
↑ L H Active Z
↑ L L Active Active
OUTPUTS
A-TO-B STORAGE
(OEB
= L)
INPUTS
CLKENA1 CLKENA2 CLK A 1B 2B
L H ↑ L L 2B
L H ↑ HH2B
L L ↑ LLL
L L ↑HHH
H L ↑L1B
H L ↑ H1B
H H X X1B
†
Output level before the indicated steady-state input
conditions were established
B-TO-A STORAGE
(OEA
= L)
INPUTS
CLK SEL 1B 2B
X H X X A
X LXX A
↑HLX L
↑HHX H
↑LXL L
↑LXH H
†
Output level before the indicated steady-state
input conditions were established
OUTPUTS
†
0
†
0
†
0
OUTPUT
A
†
0
†
0
2B
†
0
†
0
L
H
†
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
29
CLK
2
OEB1
56
OEB2
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
C1
1D
C1
1D
CLKENA1
CLKENA2
SEL
OEA
A1
30
55
28
1
8
C1
1D
C1
1D
C1
1D
1 of 12 Channels
G1
1
1
CE
C1
1D
23
1B1
6
2B1
CE
C1
1D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVCHR16269A
IOHHigh-level output current
mA
IOLLow-level output current
mA
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I/O ports (see Notes 1 and 2) –0.5 V to V
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
∆t/∆v Input transition rise or fall rate 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –2
VCC = 2.3 V –6
VCC = 2.7 V –8
VCC = 3 V –12
VCC = 1.65 V 2
VCC = 2.3 V 6
VCC = 2.7 V 8
VCC = 3 V 12
CC
1.7
CC
CC
V
CC
V
V
V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
mA
I
mA
1.65 V
2.3 V
()
3 V
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –2 mA 1.65 V 1.2
IOH = –4 mA 2.3 V 1.9
V
OH
V
OL
I
I
I
I(hold)
§
I
OZ
I
CC
∆I
CC
C
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
Control inputs VI = VCC or GND 3.3 V 5 pF
i
A or B ports VO = VCC or GND 3.3 V 8.5 pF
io
= –6
OH
IOH = –8 mA 2.7 V 2
IOH = –12 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 2 mA 1.65 V 0.45
IOL = 4 mA 2.3 V 0.4
= 6
OL
IOL = 8 mA 2.7 V 0.6
IOL = 12 mA 3 V 0.8
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V
VI = 1.07 V
VI = 0.7 V
VI = 1.7 V
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
‡
V
CC
2.3 V 1.7
3 V 2.4
2.3 V 0.55
3 V 0.55
3.6 V ±500
MIN TYP†MAX UNIT
25
–25
45
–45
75
–75
V
V
µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ALVCHR16269A
(INPUT)
(OUTPUT)
tpdCLK
ns
t
CLK
ns
t
CLK
ns
PARAMETER
TEST CONDITIONS
UNIT
C
C
pF
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
f
clock
t
w
t
su
t
h
†
This information was not available at the time of publication.
Clock frequency
Pulse duration, CLK high or low
A data before CLK↑
B data before CLK↑
Setup time
Hold time
SEL
before CLK↑
CLKENA1 or CLKENA2 before CLK↑
OE before CLK↑
A data after CLK↑
B data after CLK↑
SEL
after CLK↑
CLKENA1 or CLKENA2 after CLK↑
OE after CLK↑
VCC = 1.8 V
MIN MAX MIN MAX MIN MAX MIN MAX
†
†
†
†
†
†
†
†
†
†
†
VCC = 2.5 V
± 0.2 V
†
5.2 4.3 3.3 ns
1.4 1.4 1
1.6 1.5 1.1
0.8 1.1 1.3
0.8 1 0.8
1.7 1.6 1.2
0.9 0.9 1.2
0.8 0.6 1
1.1 0.8 1.7
1.4 1 1.6
0.9 0.8 1.2
VCC = 2.7 V
95 115 135 MHz
VCC = 3.3 V
± 0.3 V
UNIT
ns
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
f
max
en
dis
†
This information was not available at the time of publication.
operating characteristics, T
Power dissipation
pd
capacitance
†
This information was not available at the time of publication.
FROM
= 25°C
A
All outputs enabled
All outputs disabled
TO
B
A
B
A
B
A
VCC = 1.8 V
MIN TYP MIN MAX MIN MAX MIN MAX
†
= 0,f = 10 MHz
L
VCC = 2.5 V
± 0.2 V
95 115 135 MHz
†
2.3 7.7 6.9 2.2 5.8
†
1.9 6.4 5.8 2 5.2
†
2.5 7.7 6.9 2.3 5.8
†
2.2 6.7 6 2.1 5.3
†
3.3 8.1 6.7 2.4 6
†
2.7 8 6.2 2.1 6
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
VCC = 2.7 V
TYP TYP TYP
†
†
142 172
115 129
VCC = 3.3 V
± 0.3 V
UNIT
p
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
SCES050L – AUGUST 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1 kΩ
1 kΩ
S1
SN74ALVCHR16269A
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74ALVCHR16269A
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES050L – AUGUST 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
SCES050L – AUGUST 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
500 Ω
500 Ω
S1
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
SN74ALVCHR16269A
WITH 3-STATE OUTPUTS
Open
6 V
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
VOLTAGE WAVEFORMS
and t
PHZ
and t
PZH
and t
PHL
1.5 V
t
su
1.5 V 1.5 V
are the same as t
are the same as ten.
are the same as tpd.
h
1.5 V
.
dis
t
PHL
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
V
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
2.7 V
0 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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Copyright 1999, Texas Instruments Incorporated
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