Texas Instruments SN74ALVCHG162282DBBR, SN74ALVCHG162282GR Datasheet
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Sub-Micron Process
D
A-Port Outputs Have Equivalent 50-Ω
Series Resistors and B-Port Outputs Have
Equivalent 20-Ω Series Resistors, So No
External Resistors Are Required
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus-Hold On Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Packaged in Thin Very Small-Outline
Package
NOTE: For order entry:
The DBB package is abbreviated to G.
For tape and reel:
The DBBR package is abbreviated to GR.
description
The SN74ALVCHG162282 is an 18-bit to 36-bit
registered bus exchanger. This device is intended
for use in applications where data must be
transferred from a narrow high-speed bus to a
wide lower-frequency bus. It is designed
specifically for low-voltage (3.3-V) V
CC
operation.
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input. For data transfer in the
B-to-A direction, the select (SEL
) input selects 1B
or 2B data for the A outputs.
For data transfer in the A-to-B direction, a
two-stage pipeline is provided in the 1B path, with
a single storage register in the 2B path. Data flow
is controlled by the active-low output-enable (OE)
and direction-control (DIR) input. DIR is registered
to synchronize the bus direction changes with the
clock.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC are trademarks of Texas Instruments Incorporated.
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V
CC
GND
2B9
1B9
2B8
GND
1B8
2B7
1B7
V
CC
2B6
1B6
2B5
1B5
GND
2B4
1B4
2B3
1B3
V
CC
GND
2B2
1B2
2B1
1B1
V
CC
A1
A2
A3
GND
A4
A5
A6
V
CC
A7
A8
A9
GND
CLK
SEL
V
CC
GND
1B10
2B10
1B11
GND
2B11
1B12
2B12
V
CC
1B13
2B13
1B14
2B14
GND
1B15
2B15
1B16
2B16
V
CC
GND
1B17
2B17
1B18
2B18
V
CC
A18
A17
A16
GND
A15
A14
A13
V
CC
A12
A11
A10
GND
OE
DIR
DBB PACKAGE
(TOP VIEW)
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The A-port N-channel output transistors are sized at 450 µm and the P-channel output transistors are sized at
700 µm. All A-port outputs have equivalent 50-Ω series resistors. The B-port N-channel output transistors are
sized at 225 µm, and the P-channel output transistors are sized at 560 µm. All B-port outputs have equivalent
20-Ω series resistors.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The switching characteristics are based on 25-pF (A port) and 80-pF (B port) loads, but are tested with the
standard 50-pF load.
The SN74ALVCHG162282 is characterized for operation from 0°C to 70°C.
Function Tables
A-TO-B STORAGE
(OE
= L, DIR = H)
INPUTS
OUTPUTS
SEL CLK A 1B 2B
H X X 1B
0
†
2B
0
†
L ↑ LL‡L
L ↑ H H
‡
H
†
Output level before indicated
steady-state input conditions were
established
‡
Two CLK edges are needed to propagate
the data.
B-TO-A STORAGE
(OE
= L, DIR = L)
INPUTS
OUTPUT
CLK SEL 1B 2B
A
↑ H X L L
§
↑ HXH H
§
↑ LLX L
↑ L H X H
§
Two CLK edges are needed to propagate the
data. The data is loaded in the first register
when SEL
is low and propagates to the
second register when SEL
is high.
OUTPUT ENABLE
INPUTS
OUTPUTS
CLK OE DIR A 1B, 2B
↑ H X Z Z
↑ LHZActive
↑ L L Active Z
SN74ALVCHG162282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES094C – FEBRUARY 1997 – REVISED JUNE 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
C1
1D
C1
1D
G1
1
1
C1
CE
1D
C1
CE
C1
CE
1D
1D
C1
CE
1D
1 of 18 Channels
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41
27
25
24
CLK
SEL
OE
DIR
A1
1B1
2B1
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