Texas Instruments SN74ALVCH244DW, SN74ALVCH244DWR, SN74ALVCH244PWLE, SN74ALVCH244PWR, SN74ALVCH244DGVR Datasheet
SN74ALVCH244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES112C – JULY 1997 – REVISED FEBRUARY 1999
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic
Small-Outline (DW, NS), Thin Very
DGV, DW, NS, OR PW PACKAGE
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
(TOP VIEW)
1
20
2
19
3
18
4
17
5
16
6
15
7
14
8
13
9
12
10
11
V
CC
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
2A1
Small-Outline (DGV), and Thin Shrink
Small-Outline (PW) Packages
description
This octal buffer/line driver is designed for 1.65-V to 3.6-V VCC operation.
The SN74AL VCH244 is organized as two 4-bit line drivers with separate output-enable (OE
is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
) inputs. When OE
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OE A
L H H
L LL
HXZ
OUTPUT
Y
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74ALVCH244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES112C – JULY 1997 – REVISED FEBRUARY 1999
logic symbol
1OE
1A1
1A2
1A3
1A4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
1
2
4
6
8
EN
18
16
14
12
1Y1
1Y2
1Y3
1Y4
2OE
2A1
2A2
2A3
2A4
logic diagram (positive logic)
1
1OE
218
1A1
416
1A2
1Y1
1Y2
2OE
2A1
2A2
19
11
13
15
17
19
11 9
13 7
EN
2Y1
2Y2
9
2Y1
7
2Y2
5
2Y3
3
2Y4
614
1A3
812
1A4
1Y3
1Y4
15 5
2A3
17 3
2A4
2Y3
2Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through V
Package thermal impedance, θ
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGV package 146°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 100°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 128°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
‡
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74ALVCH244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES112C – JULY 1997 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
∆t/∆v Input transition rise or fall rate 5 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –4
VCC = 2.3 V –12
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 12
VCC = 2.7 V 12
VCC = 3 V 24
CC
1.7
0.7
CC
CC
V
CC
V
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVCH244
V
V
I
mA
()
C
V
V
GND
3.3 V
pF
(INPUT)
(OUTPUT)
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES112C – JULY 1997 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
V
OH
IOH = –12 mA
IOH = –24 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
OL
I
I
I
I(hold)
I
OZ
I
CC
∆I
CC
Control inputs
i
Data inputs
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
This information was not available at the time of publication.
Outputs VO = VCC or GND 3.3 V 8 pF
o
IOL = 6 mA 2.3 V 0.4
= 12
OL
IOL = 24 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V
VI = 1.07 V 1.65 V
VI = 0.7 V 2.3 V 45
VI = 1.7 V 2.3 V –45
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
CC
‡
or
VI = 0 to 3.6 V
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 10 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
=
I
V
CC
2.3 V 1.7
2.7 V 2.2
3 V 2.4
2.3 V 0.7
2.7 V 0.4
3.6 V ±500
MIN TYP†MAX UNIT
§
§
4.5
6
V
µA
p
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
t
pd
t
en
t
dis
§
This information was not available at the time of publication.
4
FROM
A
OE
OE
TO
Y
Y
Y
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 1.8 V
TYP MIN MAX MIN MAX MIN MAX
§ 1 3.1 3.1 1.1 2.8 ns
§
§
VCC = 2.5 V
± 0.2 V
1.5 5.4 5.3 1.5 4.5 ns
1 4.1 4.4 1.7 4.2 ns
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
CONDITIONS
C
C
pF
SN74ALVCH244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES112C – JULY 1997 – REVISED FEBRUARY 1999
operating characteristics, T
PARAMETER
Power dissipation capacitance
pd
per buffer/driver
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
TEST
= 0, f = 10 MHz
L
†
†
VCC = 2.5 V
± 0.2 V
22 28
1.5 4
VCC = 1.8 V
TYP TYP TYP
VCC = 3.3 V
± 0.3 V
UNIT
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ALVCH244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES112C – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
1 kΩ
1 kΩ
S1
V
2 × V
Open
GND
= 1.8 V
CC
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at Open
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
SCES112C – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
500 Ω
500 Ω
S1
SN74ALVCH244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74ALVCH244
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES112C – JULY 1997 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
S1
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
Timing
Input
Data
Input
Input
Output
t
PLH
LOAD CIRCUIT
1.5 V
t
su
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
1.5 V
t
PHL
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
w
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 3. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
.
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