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SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit bus transceiver is designed for 1.65-V
to 3.6-V V
The SN74ALVCH16863 is an 18-bit noninverting
transceiver designed for synchronous
communication between data buses. The
control-function implementation minimizes
external timing requirements.
The SN74AL VCH16863 can be used as two 9-bit
transceivers or one 18-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the output-enable (OEAB
inputs.
operation.
CC
or OEBA)
DGG OR DL PACKAGE
(TOP VIEW)
1B1
1B2
1B3
1B4
V
1B5
1B6
1B7
1B8
1B9
2B1
2B2
2B3
2B4
2B5
V
2B6
2B7
2B8
2B9
CC
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
1OEAB
GND
GND
GND
GND
GND
GND
2OEAB
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2A8
2A9
2OEBA
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16863 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit section)
INPUTS
OEAB OEBA
H L B data to A bus
L H A data to B bus
H H Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
logic symbol
†
1OEBA
1OEAB
2OEBA
2OEAB
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
56
1
29
28
55
54
52
51
49
48
47
45
44
41
40
38
37
36
34
33
31
30
EN1
EN2
EN3
EN4
3
16
10
12
13
17
19
20
21
23
24
26
27
2
1B1
3
1B2
5
1B3
6
1B4
8
1B5
9
1B6
1B7
1B8
1B9
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
1
1
1
2
1
1
4
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OEBA
1OEAB
2
56
1
55 2
1A1 1B1
To Eight Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2OEBA
2OEAB
2A1 2B1
29
28
41 16
To Eight Other Channels
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I/O ports (see Notes 1 and 2) –0.5 V to V
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
∆t/∆v Input transition rise or fall rate 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –4
VCC = 2.3 V –12
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 12
VCC = 2.7 V 12
VCC = 3 V 24
CC
1.7
CC
CC
V
CC
V
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVCH16863
V
V
I
mA
()
C
V
V
GND
3.3 V
pF
(INPUT)
(OUTPUT)
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
V
OH
IOH = –12 mA
IOH = –24 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
OL
I
I
I
I(hold)
I
OZ
I
CC
∆I
CC
Control inputs
i
Data inputs
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
Outputs VO = VCC or GND 3.3 V 7.5 pF
o
IOL = 6 mA 2.3 V 0.4
= 12
OL
IOL = 24 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45
VI = 1.7 V 2.3 V –45
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
CC
‡
or
VI = 0 to 3.6 V
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
=
I
V
CC
2.3 V 1.7
2.7 V 2.2
3 V 2.4
2.3 V 0.7
2.7 V 0.4
3.6 V ±500
MIN TYP†MAX UNIT
3.5
6
V
µA
p
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
t
pd
t
en
t
dis
§
This information was not available at the time of publication.
4
FROM
A or B B or A
OEAB or OEBA
OEAB or OEBA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TO
A or B
A or B
VCC = 1.8 V
TYP MIN MAX MIN MAX MIN MAX
§
§
§
VCC = 2.5 V
± 0.2 V
1 4.1 4 1 3.4 ns
1 5.7 5.8 1 4.7 ns
1.3 5.5 4.7 1.4 4.2 ns
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
PARAMETER
TEST CONDITIONS
UNIT
C
C
pF
SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
operating characteristics, T
Power dissipation
pd
capacitance
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
Timing
Input
Data
Input
Input
Output
LOAD CIRCUIT
t
su
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
t
PLH
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1 kΩ
VCC/2
t
h
1 kΩ
S1
VCC/2
p
= 50 pF,f = 10 MHz
L
= 1.8 V
V
CC
2 × V
CC
Open
GND
V
CC
0 V
V
CC
0 V
V
CC
S1 at 2 × V
0 V
t
PHL
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
†
†
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
21 30
2 3
Open
2 × V
GND
t
w
VCC/2
VCC/2
CC
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
V
0 V
V
0 V
V
V
V
0 V
p
CC
CC
CC
OL
OH
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
V
= 2.5 V ± 0.2 V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
S1
t
PHL
6 V
GND
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
OH
V
OL
Open
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
w
1.5 V
1.5 V
Open
6 V
GND
1.5 V1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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performed, except those mandated by government requirements.
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Copyright 1999, Texas Instruments Incorporated
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