Texas Instruments SN74ALVCH16646DGGR, SN74ALVCH16646DGVR, SN74ALVCH16646DL, SN74ALVCH16646DLR Datasheet

SN74ALVCH16646

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCES032E– JULY 1995 – REVISED FEBRUAR Y 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages

description

This 16-bit bus transceiver and register is
designed for 1.65-V to 3.6-V V

CC

operation.

The SN74AL VCH16646 can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is clocked into the registers on the
low-to-high transition of the appropriate clock
(CLKAB or CLKBA) input. Figure 1 illustrates the
four fundamental bus-management functions that
can be performed with the SN74ALVCH16646.

Output-enable (OE

) and direction-control (DIR)
inputs are provided to control the transceiver
functions. In the transceiver mode, data present at
the high-impedance port may be stored in either
register or in both. The select-control (SAB and SBA) inputs can multiplex stored and real-time (transparent
mode) data. The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer
during the transition between stored and real-time data. DIR determines which bus receives data when OE

is

low. In the isolation mode (OE

high), A data may be stored in one register and/or B data may be stored in the

other register.
When an output function is disabled, the input function is still enabled and may be used to store and transmit

data. Only one of the two buses, A or B, can be driven at a time.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16646 is characterized for operation from –40°C to 85°C.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

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31
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1DIR

1CLKAB

1SAB

GND

1A1
1A2

V

CC

1A3
1A4
1A5

GND

1A6
1A7
1A8
2A1
2A2
2A3

GND

2A4
2A5
2A6

V

CC

2A7
2A8

GND

2SAB

2CLKAB

2DIR

1OE
1CLKBA
1SBA
GND
1B1
1B2
V

CC

1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V

CC

2B7
2B8
GND
2SBA
2CLKBA
2OE

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

Copyright  1999, Texas Instruments Incorporated

SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCES032E– JULY 1995 – REVISED FEBRUAR Y 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

DATA I/Os

OE

DIR CLKAB CLKBA SAB SBA A1–A8 B1–B8

OPERATION OR FUNCTION

X X ↑ X X X Input Unspecified

†

Store A, B unspecified

†

X XX ↑X X Unspecified

†

Input Store B, A unspecified

†

H X ↑ ↑ X X Input Input Store A and B data
H X H or L H or L X X Input disabled Input disabled Isolation, hold storage
L L X X X L Output Input Real-time B data to A bus
L L X H or L X H Output Input Stored B data to A bus
L H X X L X Input Output Real-time A data to B bus
L H H or L X H X Input Output Stored A data to B bus

†

The data-output functions may be enabled or disabled by various signals at OE and DIR. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition of the clock inputs.

SN74ALVCH16646

16-BIT BUS TRANSCEIVER AND REGISTER

WITH 3-STATE OUTPUTS

SCES032E– JULY 1995 – REVISED FEBRUAR Y 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

L

DIRLCLKABXCLKBAXSABXSBA

LL

DIRHCLKABXCLKBAXSABLSBA

X

X

DIRXCLKAB CLKBAXSABXSBA

X

L

DIRLCLKABXCLKBA

H or L

SABXSBA

H

X

H

X
X

XX

X

X
X

L H H or L X H X

↑

↑
↑↑

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

BUS B

BUS A

OE

OE

OEOE

REAL-TIME TRANSFER

BUS B TO BUS A

REAL-TIME TRANSFER

BUS A TO BUS B

STORAGE FROM

A, B, OR A AND B

TRANSFER STORED DATA

TO A AND/OR B

Figure 1. Bus-Management Functions

SN74ALVCH16646
16-BIT BUS TRANSCEIVER AND REGISTER
WITH 3-STATE OUTPUTS

SCES032E– JULY 1995 – REVISED FEBRUAR Y 1999

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic symbol

†

1A2

6

1A3

8

1A4

9

1A5

10

1A6

12

1A7

13

1A8

14

2A2

16

2A3

17

2A4

19

2A5

20

2A6

21

2A7

23

2A8

24

5

1A1

1B6

45

1B7

44

1B8

43

1B2

51

1B3

49

1B4

48

1B5

47

1B1

52

4D

1

2

G12

31

2SBA

30

2CLKBA

10 EN8 [BA]

28

2DIR

G10

29

2B6

36

2B7

34

2B8

33

2B2

41

2B3

40

2B4

38

2B5

37

2OE

10 EN9 [AB]

≥1

155

≥1

177

15

2A1

8

9

≥1

11212

≥1

11414

13D

2B1

42

11D

C11

G14

26

2SAB

27

2CLKAB

C13

G5

54

1SBA

55

1CLKBA

3 EN1 [BA]

1

1DIR

G3

56

1OE

3 EN2 [AB]

C4

G7

3

1SAB

2

1CLKAB

C6

6D

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.