Texas Instruments SN74ALVCH16600DGGR, SN74ALVCH16600DL, SN74ALVCH16600DLR Datasheet

SN74ALVCH16600
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES030E – JULY 1995 – REVISED MAY 2000
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Mode
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per JESD 17
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
description
This 18-bit universal bus transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74AL VCH16600 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB and CLKENBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB
is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output enable OEAB is active low. When OEAB is low, the outputs are active. When OEAB is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, CLKBA, and CLKENBA. T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16600 is characterized for operation from –40°C to 85°C.
Copyright 2000, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
DGG OR DL PACKAGE
(TOP VIEW)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
OEAB
LEAB
A1
GND
A2 A3
V
CC
A4 A5 A6
GND
A7 A8
A9 A10 A11 A12
GND
A13 A14 A15
V
CC
A16 A17
GND
A18
OEBA
LEBA
CLKENAB CLKAB B1 GND B2 B3 V
CC
B4 B5 B6 GND B7 B8 B9 B10 B11 B12 GND B13 B14 B15 V
CC
B16 B17 GND B18 CLKBA CLKENBA
EPIC, UBT, and Widebus are trademarks of Texas Instruments.
SN74ALVCH16600 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS
SCES030E – JULY 1995 – REVISED MAY 2000
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUT
CLKENAB OEAB
LEAB
CLKAB
A
B
X H X X X Z X LH XL L X LH XH H H LL XXB
0
H LL XXB
0
L LL LL L LL HH L LL HXB
0
L L L L X B
0
§
A-to-B data flow is shown; B-to-A flow is similar but uses OEBA
, LEBA, and CLKBA.
Output level before the indicated steady-state input conditions were established, provided that CLKAB was high before LEAB went low
§
Output level before the indicated steady-state input conditions were established
SN74ALVCH16600
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES030E – JULY 1995 – REVISED MAY 2000
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
logic diagram (positive logic)
CE
1D C1
CLK
CE 1D C1
CLK
B1
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
3
54
To 17 Other Channels
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