Texas Instruments SN74ALVCH16525DLR, SN74ALVCH16525DGGR, SN74ALVCH16525DL Datasheet
SN74ALVCH16525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES059D – NOVEMBER 1995 – REVISED SEPTEMBER 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Option Includes Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V VCC operation.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA) and
clock-enable (CLKENAB
and CLKENBA) inputs.
For the A-to-B data flow, the data flows through a
single register. The B-to-A data can flow through
a four-stage pipeline register path, or through a
single register path, depending on the state of the
select (SEL
) input.
Data is stored in the internal registers on the
low-to-high transition of the clock (CLK) input,
provided that the appropriate CLKEN inputs are
low. The A-to-B data transfer is synchronized to
the CLKAB input, and B-to-A data transfer is
synchronized with the CLK1BA and CLK2BA
inputs.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16525 is characterized for operation from –40°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
DGG OR DL PACKAGE
(TOP VIEW)
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CLKENAB
OEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
CLKENBA
SEL
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLK1BA
CLK2BA
SN74ALVCH16525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES059D – NOVEMBER 1995 – REVISED SEPTEMBER 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
A-TO-B STORAGE
(OEAB
= L)
INPUTS
OUTPUT
CLKENAB CLKAB A
B
H X X B
0
†
L ↑ LL
L ↑ H H
†
Output level before the indicated steady-state
input conditions were established
B-TO-A STORAGE
(OEBA
= L)
INPUTS
OUTPUT
CLKENBA CLK2BA CLK1BA SEL B
A
H X X X X A
0
†
L ↑ XHL L
L ↑ XHHH
L ↑↑LL L
‡
L ↑ ↑ L H H
‡
†
Output level before the indicated steady-state input conditions were
established
‡
Three CLK1BA edges and one CLK2BA edge are needed to
propagate data from B to A when SEL
is low.
SN74ALVCH16525
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES059D – NOVEMBER 1995 – REVISED SEPTEMBER 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
B1
CLKAB
CLK1BA
CLK2BA
CLKENBA
CLKENAB
OEAB
OEBA
SEL
CE
C1
1D
A1
CE
C1
1D
CE
C1
1D
CE
C1
1D
CE
C1
1D
1
1
1 of 18 Channels
G1
55
30
29
28
1
2
27
56
3
54
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