Texas Instruments SN74ALVCH16524DGGR, SN74ALVCH16524DL, SN74ALVCH16524DLR Datasheet

SN74ALVCH16524

18-BIT REGISTERED BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES080C – JULY 1996 – REVISED FEBRUARY 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

description

This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V V

CC

operation.

Data flow in each direction is controlled by
output-enable (OEAB

and OEBA) and

clock-enable (CLKENBA

) inputs. For the A-to-B
data flow, the data flows through a single buffer.
The B-to-A data can flow through a four-stage
pipeline register path, or through a single register
path, depending on the state of the select (SEL

)

input.
Data is stored in the internal registers on the

low-to-high transition of the clock (CLK) input,
provided that the appropriate CLKENBA

input is
low. The B-to-A data transfer is synchronized with
CLK.

T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16524 is characterized for operation from –40°C to 85°C.

Copyright  1999, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

GND

OEAB

A1

GND

A2
A3

V

CC

A4
A5
A6

GND

A7
A8
A9

A10

A1 1

A12

GND

A13
A14
A15

V

CC

A16
A17

GND

A18

OEBA

CLKENBA

GND
SEL
B1
GND
B2
B3
V

CC

B4
B5
B6
GND
B7
B8
B9
B10
B1 1
B12
GND
B13
B14
B15
V

CC

B16
B17
GND
B18
CLK
GND

SN74ALVCH16524
18-BIT REGISTERED BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES080C – JULY 1996 – REVISED FEBRUARY 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

B-TO-A STORAGE (OEBA

= L)

INPUTS

OUTPUT

CLKENBA CLK SEL B

A

H X X X A

0

†

L ↑ HL L
L ↑ HH H
L ↑ LLL

‡

L ↑ LHH

‡

†

Output level before the indicated steady-state input
conditions were established

‡

Four positive CLK edges are needed to propagate data
from B to A when SEL

is low.

logic diagram (positive logic)

B1

CLK

CLKENBA

OEAB

OEBA

SEL

CE

C1

1D

A1

CE

C1

1D

CE

C1

1D

CE

C1

1D

1
1

1 of 18 Channels

G1

30

28

2

27

55

3 54

SN74ALVCH16524

18-BIT REGISTERED BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES080C – JULY 1996 – REVISED FEBRUARY 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, V

CC

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, V

I

: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I/O ports (see Notes 1 and 2) –0.5 V to V

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, I

IK

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, I

OK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, I

O

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each V

CC

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

recommended operating conditions (see Note 4)

MIN MAX UNIT

V

CC

Supply voltage 1.65 3.6 V

VCC = 1.65 V to 1.95 V 0.65 × V

CC

V

IH

High-level input voltage

VCC = 2.3 V to 2.7 V

1.7

V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V

CC

V

IL

Low-level input voltage

VCC = 2.3 V to 2.7 V 0.7

V
VCC = 2.7 V to 3.6 V 0.8

V

I

Input voltage 0 V

CC

V

V

O

Output voltage 0 V

CC

V
VCC = 1.65 V –4

p

VCC = 2.3 V –12

IOHHigh-level output current

VCC = 2.7 V –12

mA

VCC = 3 V –24
VCC = 1.65 V 4

p

VCC = 2.3 V 12

IOLLow-level output current

VCC = 2.7 V 12

mA

VCC = 3 V 24

∆t/∆v Input transition rise or fall rate 10 ns/V
T

A

Operating free-air temperature –40 85 °C

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.