Datasheet SN74ALVCH16501DGGR, SN74ALVCH16501DL, SN74ALVCH16501DLR Datasheet (Texas Instruments)
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V VCC operation.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB
is low, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLKAB. When OEAB
is high, the outputs are active. When OEAB is low,
the outputs are in the high-impedance state.
DGG OR DL PACKAGE
(TOP VIEW)
OEAB
LEAB
GND
GND
GND
GND
OEBA
LEBA
V
A10
A11
A12
A13
A14
A15
V
A16
A17
A18
A1
A2
A3
CC
A4
A5
A6
A7
A8
A9
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
Data flow for B to A is similar to that of A to B, but uses OEBA
, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
To ensure the high-impedance state during power up or power down, OEBA should be tied to VCC through a
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16501 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, UBT, and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
FUNCTION TABLE
INPUTS
OEAB LEAB CLKAB A
L X X X Z
H HXLL
H HXHH
H L ↑ LL
H L ↑ HH
H LHXB
H L L X
†
A-to-B data flow is shown; B-to-A flow is similar but
uses OEBA
‡
Output level before the indicated steady-state input
conditions were established, provided that CLKAB
was high before LEAB went low
§
Output level before the indicated steady-state input
conditions were established
, LEBA, and CLKBA.
†
OUTPUT
B
‡
0
§
B
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
logic symbol
†
OEAB
CLKAB
LEAB
OEBA
CLKBA
LEBA
1
55
2
27
30
28
3
A1 B1
5
A2
6
A3
8
A4
9
A5
10
A6
12
A7
13
A8
14
A9
15
A10
16
A11
17
A12
19
A13
20
A14
21
A15
23
A16
24
A17
26
A18
EN1
C3
G2
EN4
C6
G5
3D
4
2C3
5C6
11
1
6D
54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
logic diagram (positive logic)
OEAB
CLKAB
LEAB
LEBA
CLKBA
OEBA
A1
1
55
2
28
30
27
3
CLK
1D
C1
1D
C1
CLK
54
B1
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I/O ports (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 3): DGG package 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DL package 56°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
∆t/∆v Input transition rise or fall rate 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –4
VCC = 2.3 V –12
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 12
VCC = 2.7 V 12
VCC = 3 V 24
CC
1.7
0.7
CC
CC
V
CC
V
V
V
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5
SN74ALVCH16501
V
V
I
mA
()
twPulse duration
ns
thHold time
ns
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
V
OH
IOH = –12 mA
IOH = –24 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
OL
I
I
I
I(hold)
§
I
OZ
I
CC
∆I
CC
C
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
Control inputs VI = VCC or GND 3.3 V 4 pF
i
A or B ports VO = VCC or GND 3.3 V 8 pF
io
IOL = 6 mA 2.3 V 0.4
= 12
OL
IOL = 24 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45
VI = 1.7 V 2.3 V –45
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
VI = 0 to 3.6 V
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
‡
V
CC
2.3 V 1.7
2.7 V 2.2
3 V 2.4
2.3 V 0.7
2.7 V 0.4
3.6 V ±500
MIN TYP†MAX UNIT
V
µA
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
f
clock
t
su
¶
This information was not available at the time of publication.
6
Clock frequency
Setup time
LE high
CLK high or low
Data before CLK↑
Data
before LE↓
Data after CLK↑
Data after LE↓ CLK high or low
CLK high
CLK low
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VCC = 1.8 V
MIN MAX MIN MAX MIN MAX MIN MAX
¶
¶
¶
¶
¶
¶
¶
VCC = 2.5 V
± 0.2 V
¶
3.3 3.3 3.3
3.3 3.3 3.3
2.2 2.1 1.7
1.9 1.6 1.5
1.3 1.1 1
0.6 0.6 0.7
1.4 1.7 1.4
VCC = 2.7 V
150 150 150 MHz
VCC = 3.3 V
± 0.3 V
UNIT
ns
(INPUT)
(OUTPUT)
A or B
PARAMETER
TEST CONDITIONS
UNIT
C
C
50 pF
pF
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
f
max
t
pd
t
en
t
dis
t
en
t
†
dis
This information was not available at the time of publication.
FROM
A or B B or A
LE
CLK
OEAB B
OEAB B
OEBA A
OEBA A
TO
VCC = 1.8 V
MIN TYP MIN MAX MIN MAX MIN MAX
†
VCC = 2.5 V
± 0.2 V
150 150 150 MHz
†
†
†
†
†
†
†
1 4.8 4.5 1 3.9
1.1 5.7 5.3 1.3 4.6
1.2 6.1 5.6 1.4 4.9
1 5.8 5.3 1 4.6 ns
1.5 6.2 5.7 1.4 5 ns
1.3 6.3 6 1.1 5 ns
1.3 5.3 4.6 1.3 4.2 ns
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
ns
operating characteristics, T
Power dissipation
pd
capacitance
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
p
,f = 10 MHz
=
L
†
†
44 54
6 6
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
2 × V
From Output
Under Test
CL = 30 pF
(see Note A)
1 kΩ
1 kΩ
S1
GND
V
CC
Open
= 1.8 V
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
h
VCC/2
VCC/2 VCC/2
are the same as t
are the same as ten.
are the same as tpd.
dis
.
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
8
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From Output
Under Test
(see Note A)
CL = 30 pF
18-BIT UNIVERSAL BUS TRANSCEIVER
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
Open
GND
CC
t
PLZ/tPZL
t
PHZ/tPZH
500 Ω
500 Ω
S1
SN74ALVCH16501
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
TEST S1
t
pd
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
h
VCC/2
VCC/2 VCC/2
dis
are the same as tpd.
.
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN74ALVCH16501
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES024D – JULY 1995 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
500 Ω
500 Ω
S1
6 V
GND
Open
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
6 V
GND
Timing
Input
Data
Input
Input
Output
t
PLH
LOAD CIRCUIT
1.5 V
t
su
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
1.5 V
t
PHL
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
w
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 3. Load Circuit and Voltage Waveforms
10
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.
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
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