Texas Instruments SN74ALVCH16374DGGR, SN74ALVCH16374DL, SN74ALVCH16374DLR Datasheet

SN74ALVCH16374

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES021D – JULY 1995 – REVISED FEBRUARY 1999

D

Member of the Texas Instruments

D

Widebus
EPIC

 Family

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

description

This 16-bit edge-triggered D-type flip-flop is
designed for 1.65-V to 3.6-V V

The SN74AL VCH16374 is particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers. It
can be used as two 8-bit flip-flops or one 16-bit
flip-flop. On the positive transition of the clock
(CLK) input, the Q outputs of the flip-flop take on
the logic levels at the data (D) inputs. OE
used to place the eight outputs in either a normal
logic state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
the increased drive provide the capability to drive
bus lines without need for interface or pullup
components.

operation.

CC

can be

DGG OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1OE

1Q1
1Q2

GND

1Q3
1Q4

V

CC

1Q5
1Q6

GND

1Q7
1Q8
2Q1
2Q2

GND

2Q3
2Q4

V

CC

2Q5
2Q6

GND

2Q7
2Q8

2OE

1CLK
1D1
1D2
GND
1D3
1D4
V

CC

1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V

CC

2D5
2D6
GND
2D7
2D8
2CLK

OE

does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16374 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus and EPIC are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74ALVCH16374
16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS

SCES021D – JULY 1995 – REVISED FEBRUARY 1999

FUNCTION TABLE

(each flip-flop)

INPUTS

CLK D

OE

L ↑ H H
L ↑ LL
LH or L X Q

H X X Z

OUTPUT

Q

0

logic symbol

†

1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8

1
48
24
25

47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26

1EN

2EN

1D

2D

C1

C2

11
12
13
14
16
17
19
20
22
23

2

1Q1

3

1Q2

5

1Q3

6

1Q4

8

1Q5

9

1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8

1

2

1OE

1CLK

2OE

2CLK

†

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

logic diagram (positive logic)

2

1OE

1CLK

1D1

1

48

47

C1

1D

To Seven Other Channels

2CLK

1Q1

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2OE

2D1

24

25

36

C1

1D

To Seven Other Channels

132

2Q1

IOHHigh-level output current

mA

IOLLow-level output current

mA

SN74ALVCH16374

16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCES021D – JULY 1995 – REVISED FEBRUARY 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

JA

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

recommended operating conditions (see Note 4)

MIN MAX UNIT

V

V

V

V
V

∆t/∆v Input transition rise or fall rate 10 ns/V
T

NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 1.65 3.6 V

CC

VCC = 1.65 V to 1.95 V 0.65 × V

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8

VCC = 1.65 V –4
VCC = 2.3 V –12
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 12
VCC = 2.7 V 12
VCC = 3 V 24

CC

1.7

0.7

CC
CC

V

CC

V

V
V

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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