Texas Instruments SN74ALVCH162836DGGR, SN74ALVCH162836DGVR, SN74ALVCH162836DL, SN74ALVCH162836DLR, SN74ALVCH162836GR Datasheet

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Member of the Texas Instruments

Widebus

 Family

D

EPIC

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

Output Port Has Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required

D

Designed to Comply With JEDEC 168-Pin
and 200-Pin SDRAM Buffered DIMM
Specification

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages

NOTE: For tape and reel order entry:

The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.

description

This 20-bit universal bus driver is designed for

1.65-V to 3.6-V VCC operation.
Data flow from A to Y is controlled by the

output-enable (OE) input. The device operates in
the transparent mode when the latch-enable (LE)
input is low. When LE

is high, the A data is latched
if the clock (CLK) input is held at a high or low logic
level. If LE is high, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLK.
When OE is high, the outputs are in the
high-impedance state.

The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.
T o ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162836 is characterized for operation from –40°C to 85°C.

Copyright  1999, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

OE

Y1
Y2

GND

Y3
Y4

V

CC

Y5
Y6
Y7

GND

Y8

Y9
Y10
Y11
Y12
Y13

GND

Y14
Y15
Y16

V

CC

Y17
Y18

GND

Y19
Y20

NC

CLK
A1
A2
GND
A3
A4
V

CC

A5
A6
A7
GND
A8
A9
A10
A11
A12
A13
GND
A14
A15
A16
V

CC

A17
A18
GND
A19
A20
LE

NC – No internal connection

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

SN74ALVCH162836
20-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUT

OE LE CLK A

Y

H X X X Z
L LXL L
L LXH H
L H ↑ LL
L H ↑ HH
L H L or H X Y

0

†

†

Output level before the indicated steady-state
input conditions were established

logic symbol

‡

A1

55

A2

54

A3

52

A4

51

A5

49

A6

48

A7

47

A8

45

A9

44

A10

43

A11

42

A12

41

A13

40

A14

38

A15

37

A16

36

A17

34

A18

33

OE

EN1

1
56

CLK

2

Y1

3

Y2

5

Y3

1

6

Y4

8

Y5

9

Y6

10

Y7

12

Y8

13

Y9

14

Y10

15

Y11

16

Y12

17

Y13

19

Y14

20

Y15

21

Y16

23

Y17

24

Y18

C3

29

G2

LE

2C3

113D

A19

31

A20

30

26

Y19

27

Y20

‡

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

SN74ALVCH162836

20-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES122E – JULY 1997 – REVISED JUNE 1999

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

1

56

29

55

1D
C1

CLK

2

To 19 Other Channels

OE

CLK

LE

A1

Y1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

†

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output voltage range, V

O

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Package thermal impedance, θ

JA

(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

stg

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.