Texas Instruments SN74ALVCH162831DBBR, SN74ALVCH162831GR Datasheet
SN74ALVCH162831
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES084F – AUGUST 1996 – REVISED JUNE 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Packaged in Thin Very Small-Outline
Package
NOTE: For tape and reel order entry:
The DBBR package is abbreviated to GR.
description
This 1-bit to 4-bit address register/driver is
designed for 1.65-V to 3.6-V V
CC
operation.
The device is ideal for use in applications in which
a single address bus is driving four separate
memory locations. The SN74ALVCH162831 can
be used as a buffer or a register , depending on the
logic level of the select (SEL
) input.
When SEL
is logic high, the device is in the buffer
mode. The outputs follow the inputs and are
controlled by the two output-enable (OE
) inputs.
Each OE
controls two groups of nine outputs.
When SEL
is logic low, the device is in the register
mode. The register is an edge-triggered D-type
flip-flop. On the positive transition of the clock
(CLK) input, data set up at the A inputs is stored
in the internal registers. OE
controls operate the
same as in buffer mode.
When OE
is logic low, the outputs are in a normal
logic state (high or low logic level). When OE
is
logic high, the outputs are in the high-impedance
state.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
DBB PACKAGE
(TOP VIEW)
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4Y1
3Y1
GND
2Y1
1Y1
V
CC
NC
A1
GND
NC
A2
GND
NC
A3
V
CC
NC
A4
GND
CLK
OE1
OE2
SEL
GND
A5
A6
V
CC
A7
NC
GND
A8
NC
GND
A9
NC
V
CC
4Y9
3Y9
GND
2Y9
1Y9
1Y2
2Y2
GND
3Y2
4Y2
V
CC
1Y3
2Y3
GND
3Y3
4Y3
GND
1Y4
2Y4
V
CC
3Y4
4Y4
GND
1Y5
2Y5
3Y5
4Y5
GND
1Y6
2Y6
V
CC
3Y6
4Y6
GND
1Y7
2Y7
GND
3Y7
4Y7
V
CC
1Y8
2Y8
GND
3Y8
4Y8
NC – No internal connection
SN74ALVCH162831
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES084F – AUGUST 1996 – REVISED JUNE 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
SEL and OE do not affect the internal operation of the flip-flops. Old data can be retained or new data can be
entered while the outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162831 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUT
OE SEL CLK A
Y
H X X X Z
L HXL L
LHXH H
LL↑LL
LL↑HH
logic diagram (positive logic)
20
21
19
8
CLK
D Q
22
To Eight Other Channels
5
4
2
1
OE1
OE2
CLK
A1
SEL
1Y1
2Y1
3Y1
4Y1
SN74ALVCH162831
1-BIT TO 4-BIT ADDRESS REGISTER/DRIVER
WITH 3-STATE OUTPUTS
SCES084F – AUGUST 1996 – REVISED JUNE 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3) 106°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 1.65 3.6 V
VCC = 1.65 V to 1.95 V 0.65 × V
CC
V
IH
High-level input voltage
VCC = 2.3 V to 2.7 V 1.7
V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
CC
V
IL
Low-level input voltage
VCC = 2.3 V to 2.7 V
0.7
V
VCC = 2.7 V to 3.6 V 0.8
V
I
Input voltage 0 V
CC
V
V
O
Output voltage 0 V
CC
V
VCC = 1.65 V –2
p
VCC = 2.3 V –6
IOHHigh-level output current
VCC = 2.7 V –8
mA
VCC = 3 V –12
VCC = 1.65 V 2
p
VCC = 2.3 V 6
IOLLow-level output current
VCC = 2.7 V 8
mA
VCC = 3 V 12
∆t/∆v Input transition rise or fall rate 10 ns/V
T
A
Operating free-air temperature –40 85 °C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
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