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SN74ALVCH16282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES036D – JULY 1995 – REVISED MARCH 2000
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Packaged in Thin Very Small-Outline
Package
NOTE: For tape and reel order entry:
The DBBR package is abbreviated to GR.
description
The SN74ALVCH16282 is an 18-bit to 36-bit
registered bus exchanger designed for 1.65-V to
3.6-V VCC operation.
This device is intended for use in applications in
which data must be transferred from a narrow
high-speed bus to a wide lower-frequency bus. It
is designed specifically for low-voltage (3.3-V)
V
operation.
CC
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input. For data transfer in the
B-to-A direction, the select (SEL) input selects 1B
or 2B data for the A outputs.
For data transfer in the A-to-B direction, a
two-stage pipeline is provided in the 1B path, with
a single storage register in the 2B path. Data flow
is controlled by the active-low output enable (OE
and the DIR input. The DIR control pin is
registered to synchronize the bus direction
changes with the clock.
Active bus-hold circuitry is provided to hold
unused or floating data inputs at a valid logic level.
DBB PACKAGE
(TOP VIEW)
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41
V
CC
GND
1B10
2B10
1B11
GND
2B11
1B12
2B12
V
CC
1B13
2B13
1B14
2B14
GND
1B15
2B15
1B16
2B16
V
CC
GND
1B17
2B17
1B18
2B18
V
CC
A18
A17
A16
GND
A15
A14
A13
V
CC
A12
A11
A10
GND
OE
DIR
V
CC
GND
2B9
1B9
2B8
GND
1B8
2B7
1B7
V
CC
2B6
1B6
2B5
1B5
GND
2B4
1B4
2B3
1B3
V
CC
GND
2B2
1B2
2B1
1B1
V
CC
A1
A2
A3
GND
A4
A5
A6
V
CC
A7
)
A8
A9
GND
CLK
SEL
The SN74ALVCH16282 is characterized for
operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 2000, Texas Instruments Incorporated
1
SN74ALVCH16282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES036D – JULY 1995 – REVISED MARCH 2000
Function Tables
A-TO-B STORAGE (OE = L, DIR = H)
INPUTS
SEL CLK A 1B 2B
H X X 1B
L ↑ LL‡X
L ↑ H H
†
Output level before indicated
steady-state input conditions were
established
‡
Two CLK edges are needed to propagate
the data.
OUTPUTS
†
2B
0
‡
†
0
X
B-TO-A STORAGE (OE
INPUTS
CLK SEL 1B 2B
↑ H X L L
↑ HXH H
↑ LLX L
↑ L H X H
§
Two CLK edges are needed to propagate the
data. The data is loaded in the first register
when SEL
second register when SEL
CLK OE DIR A 1B, 2B
is low and propagates to the
OUTPUT ENABLE
INPUTS
↑ H X Z Z
↑ LHZActive
↑ L L Active Z
= L, DIR = L)
OUTPUT
A
§
is high.
OUTPUTS
§
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
39
CLK
40
SEL
42
OE
SN74ALVCH16282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES036D – JULY 1995 – REVISED MARCH 2000
CE
DIR
A1
41
27
C1
1D
1 of 18 Channels
C1
1D
C1
1D
G1
25
1B1
CE
CE
1D
CE
1D
C1
C1
C1
1D
24
2B1
1
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVCH16282
IOHHigh-level output current
mA
IOLLow-level output current
mA
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES036D – JULY 1995 – REVISED MARCH 2000
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I/O ports (see Notes 1 and 2) –0.5 V to V
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
JA
stg
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3) 64°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
∆t/∆v Input transition rise or fall rate 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –4
VCC = 2.3 V –12
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 12
VCC = 2.7 V 12
VCC = 3 V 24
CC
1.7
0.7
CC
CC
V
CC
V
V
V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
I
mA
()
SN74ALVCH16282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES036D – JULY 1995 – REVISED MARCH 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
V
OH
IOH = –12 mA
IOH = –24 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
OL
I
I
I
I(hold)
§
I
OZ
I
CC
∆I
CC
C
Control inputs VI = VCC or GND 3.3 V 4 pF
i
C
A or B ports VO = VCC or GND 3.3 V 8.5 pF
io
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
IOL = 6 mA 2.3 V 0.4
= 12
OL
IOL = 24 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45
VI = 1.7 V 2.3 V –45
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
VI = 0 to 3.6 V
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
‡
V
CC
2.3 V 1.7
2.7 V 2.2
3 V 2.4
2.3 V 0.7
2.7 V 0.4
3.6 V ±500
MIN TYP†MAX UNIT
V
µA
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ALVCH16282
tsuSetup time
ns
thHold time
ns
(INPUT)
(OUTPUT)
tpdCLK
ns
t
OE
ns
t
OE
ns
PARAMETER
TEST CONDITIONS
UNIT
CpdPower dissipation capacitance
C
pF
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES036D – JULY 1995 – REVISED MARCH 2000
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
VCC = 2.5 V
± 0.2 V
†
3.3 3.3 3.3 ns
2.4 2.3 2
2.2 2.2 1.8
2.2 2.1 1.7
2 2 1.8
0.5 0.5 0.7
0.5 0.5 0.6
0.5 0.5 0.5
0.7 0.7 0.8
VCC = 2.7 V
150 150 150 MHz
f
clock
t
w
†
This information was not available at the time of publication.
Clock frequency
Pulse duration, CLK high or low
p
A data before CLK↑
B data before CLK↑
DIR before CLK↑
SEL before CLK↑
A data after CLK↑
B data after CLK↑
DIR after CLK↑
SEL after CLK↑
VCC = 1.8 V
MIN MAX MIN MAX MIN MAX MIN MAX
†
†
†
†
†
†
†
†
†
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
f
max
en
dis
†
This information was not available at the time of publication.
FROM
TO
A
B
A
B
A
B
VCC = 1.8 V
MIN TYP MIN MAX MIN MAX MIN MAX
†
VCC = 2.5 V
± 0.2 V
150 150 150 MHz
†
†
†
†
†
†
1 6.1 5.5 1.4 5
1.2 6.3 5.7 1.6 5.3
1.3 6.9 6.3 1.2 5.7
2.3 8.7 8.1 2.3 7.4
1.5 7 5.6 1.8 5.7
2.1 7.9 6.4 2.3 6.4
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.3 V
UNIT
UNIT
operating characteristics, T
†
This information was not available at the time of publication.
6
= 25°C
A
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
p
p
Outputs enabled
Outputs disabled
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
= 0,f = 10 MHz
L
†
†
282 310
208 228
p
From Output
Under Test
(see Note A)
CL = 30 pF
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
SCES036D – JULY 1995 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
CC
Open
GND
1 kΩ
1 kΩ
S1
SN74ALVCH16282
WITH 3-STATE OUTPUTS
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
h
VCC/2
VCC/2 VCC/2
dis
are the same as tpd.
.
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74ALVCH16282
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES036D – JULY 1995 – REVISED MARCH 2000
PARAMETER MEASUREMENT INFORMATION
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
PROPAGATION DELAY TIMES
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
h
VCC/2
VCC/2 VCC/2
dis
are the same as tpd.
.
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
18-BIT TO 36-BIT REGISTERED BUS EXCHANGER
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
6 V
500 Ω
500 Ω
S1
Open
GND
t
SN74ALVCH16282
WITH 3-STATE OUTPUTS
SCES036D – JULY 1995 – REVISED MARCH 2000
TEST S1
t
pd
t
PLZ/tPZL
PHZ/tPZH
Open
6 V
GND
Timing
Input
Data
Input
Input
Output
LOAD CIRCUIT
t
su
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PLH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5 V
t
w
2.7 V
2.7 V
0 V
t
h
2.7 V
1.5 V
0 V
2.7 V
0 V
t
PHL
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
1.5 V
t
PZH
1.5 V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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Copyright 2000, Texas Instruments Incorporated
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