Texas Instruments SN74ALVCH16271DGGR, SN74ALVCH16271DL, SN74ALVCH16271DLR Datasheet
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 12-bit to 24-bit bus exchanger is designed for
1.65-V to 3.6-V V
The SN74ALVCH16271 is intended for
applications in which two separate data paths
must be multiplexed onto, or demultiplexed from,
a single data path. This device is particularly
suitable as an interface between conventional
DRAMs and high-speed microprocessors.
A data is stored in the internal A-to-B registers on
the low-to-high transition of the clock (CLK) input,
provided that the clock-enable (CLKENA
are low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a
24-bit word on the B port.
operation.
CC
) inputs
DGG OR DL PACKAGE
(TOP VIEW)
OEA
1
56
LE1B
GND
GND
GND
GND
LE2B
2B3
2B2
2B1
V
CC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1 1
A12
V
CC
1B1
1B2
1B3
SEL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEB
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B1 1
2B12
1B12
1B1 1
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput.
These latches transfer data when the latch-enable (LE
data for the A outputs. Data flow is controlled by the active-low output enables (OEA
) inputs are low. The select (SEL) line selects 1B or 2B
, OEB).
T o ensure the high-impedance state during power up or power down, the output enables should be tied to V
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16271 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
CC
1
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
Function Tables
OUTPUT ENABLE
INPUTS
OEA OEB A 1B, 2B
H H Z Z
H LZActive
L H Active Z
L L Active Active
A-TO-B STORAGE (OEB = L)
INPUTS
CLKENA1 CLKENA2 CLK A 1B 2B
H H X X 1B
L X ↑ LLX
L X ↑HHX
X L ↑LXL
X L ↑HA
OUTPUTS
OUTPUTS
†
2B
0
0
†
0
H
B-TO-A STORAGE (OEA = L)
INPUTS
LE SEL 1B 2B
H X X X A
H XXX A
LHLX L
LHHX H
LLXL L
LLXH H
†
Output level before the indicated steady-state
input conditions were established
OUTPUT
A
†
0
†
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
29
CLK
LE1B
2
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
LE2B
CLKENA1
CLKENA2
OEB
SEL
OEA
A1
27
30
55
56
28
1
8
CE
1D
C1
G1
LE
23
1D
1
1
LE
1D
1B1
6
2B1
CE
1D
C1
1 of 12 Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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