Datasheet SN74ALVCH16271DGGR, SN74ALVCH16271DL, SN74ALVCH16271DLR Datasheet (Texas Instruments)
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 12-bit to 24-bit bus exchanger is designed for
1.65-V to 3.6-V V
The SN74ALVCH16271 is intended for
applications in which two separate data paths
must be multiplexed onto, or demultiplexed from,
a single data path. This device is particularly
suitable as an interface between conventional
DRAMs and high-speed microprocessors.
A data is stored in the internal A-to-B registers on
the low-to-high transition of the clock (CLK) input,
provided that the clock-enable (CLKENA
are low. Proper control of these inputs allows two
sequential 12-bit words to be presented as a
24-bit word on the B port.
operation.
CC
) inputs
DGG OR DL PACKAGE
(TOP VIEW)
OEA
1
56
LE1B
GND
GND
GND
GND
LE2B
2B3
2B2
2B1
V
CC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1 1
A12
V
CC
1B1
1B2
1B3
SEL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
OEB
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B1 1
2B12
1B12
1B1 1
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
Transparent latches in the B-to-A path allow asynchronous operation to maximize memory access throughput.
These latches transfer data when the latch-enable (LE
data for the A outputs. Data flow is controlled by the active-low output enables (OEA
) inputs are low. The select (SEL) line selects 1B or 2B
, OEB).
T o ensure the high-impedance state during power up or power down, the output enables should be tied to V
through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of
the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16271 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
CC
1
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
Function Tables
OUTPUT ENABLE
INPUTS
OEA OEB A 1B, 2B
H H Z Z
H LZActive
L H Active Z
L L Active Active
A-TO-B STORAGE (OEB = L)
INPUTS
CLKENA1 CLKENA2 CLK A 1B 2B
H H X X 1B
L X ↑ LLX
L X ↑HHX
X L ↑LXL
X L ↑HA
OUTPUTS
OUTPUTS
†
2B
0
0
†
0
H
B-TO-A STORAGE (OEA = L)
INPUTS
LE SEL 1B 2B
H X X X A
H XXX A
LHLX L
LHHX H
LLXL L
LLXH H
†
Output level before the indicated steady-state
input conditions were established
OUTPUT
A
†
0
†
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
29
CLK
LE1B
2
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
LE2B
CLKENA1
CLKENA2
OEB
SEL
OEA
A1
27
30
55
56
28
1
8
CE
1D
C1
G1
LE
23
1D
1
1
LE
1D
1B1
6
2B1
CE
1D
C1
1 of 12 Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVCH16271
IOHHigh-level output current
mA
IOLLow-level output current
mA
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I/O ports (see Notes 1 and 2) –0.5 V to V
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
†
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
∆t/∆v Input transition rise or fall rate 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –4
VCC = 2.3 V –12
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V 4
VCC = 2.3 V 12
VCC = 2.7 V 12
VCC = 3 V 24
CC
1.7
CC
CC
V
CC
V
V
V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
I
mA
()
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
V
OH
IOH = –12 mA
IOH = –24 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
OL
I
I
I
I(hold)
§
I
OZ
I
CC
∆I
CC
C
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
Control inputs VI = VCC or GND 3.3 V 3.5 pF
i
A or B ports VO = VCC or GND 3.3 V 9 pF
io
IOL = 6 mA 2.3 V 0.4
= 12
OL
IOL = 24 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45
VI = 1.7 V 2.3 V –45
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
VI = 0 to 3.6 V
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
‡
V
CC
2.3 V 1.7
2.7 V 2.2
3 V 2.4
2.3 V 0.7
2.7 V 0.4
3.6 V ±500
MIN TYP†MAX UNIT
V
µA
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
f
clock
t
w
t
su
t
h
¶
This information was not available at the time of publication.
Clock frequency
Pulse duration, CLK high or low
A before CLK↑
Setup time
Hold time
B before LE
CLKEN before CLK↑
A after CLK↑
B after LE
CLKEN after CLK↑
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 1.8 V
MIN MAX MIN MAX MIN MAX MIN MAX
¶
¶
¶
¶
¶
¶
¶
VCC = 2.5 V
± 0.2 V
¶
3.3 3.3 3.3 ns
2.6 2.1 1.7
1.7 1.5 1.3
1.6 1.3 1
0.6 0.6 0.7
0.9 0.9 1.1
1 0.9 0.9
VCC = 2.7 V
130 130 130 MHz
VCC = 3.3 V
± 0.3 V
UNIT
ns
ns
5
SN74ALVCH16271
(INPUT)
(OUTPUT)
t
ns
PARAMETER
TEST CONDITIONS
UNIT
A to B
C
C
pF
B to A
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
f
max
pd
t
en
t
dis
†
This information was not available at the time of publication.
FROM
CLK B
B
LE
SEL
OEB or OEA
OEB or OEA
TO
A
B or A
B or A
VCC = 1.8 V
MIN TYP MIN MAX MIN MAX MIN MAX
†
VCC = 2.5 V
± 0.2 V
130 130 130 MHz
†
1 6.2 5 1 4.3
†
1 5.3 4.7 1.4 4
†
1 6 5.9 1.4 4.8
†
1.1 6.4 6.2 1.3 5.2
†
1 6 6.1 1 5.1 ns
†
1.4 5.4 4.6 1.7 4.2 ns
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
operating characteristics, T
Power dissipation
pd
capacitance
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
Outputs enabled
Outputs disabled
= 0,f = 10 MHz
L
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
†
†
†
†
92 105
61 76
39 43
11 13
p
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1 kΩ
1 kΩ
S1
SN74ALVCH16271
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74ALVCH16271
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
CC
Open
GND
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
Output
500 Ω
LOAD CIRCUIT
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
PLH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
12-BIT TO 24-BIT MULTIPLEXED BUS EXCHANGER
SCES017E – JULY 1995 – REVISED FEBRUAR Y 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
500 Ω
1.5 V
S1
t
h
t
PHL
Open
GND
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
V
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
SN74ALVCH16271
WITH 3-STATE OUTPUTS
Open
6 V
GND
t
w
2.7 V
0 V
2.7 V
1.5 V1.5 V
0 V
t
PLZ
3 V
1.5 V
1.5 V
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
V
0 V
OL
OH
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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