Texas Instruments SN74ALVCH16270DGGR, SN74ALVCH16270DL, SN74ALVCH16270DLR Datasheet
SN74ALVCH16270
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES028F – JULY 1995 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V V
CC
operation.
The SN74AL VCH16270 is used in applications in
which data must be transferred from a narrow
high-speed bus to a wide lower-frequency bus.
The device provides synchronous data exchange
between the two ports. Data is stored in the
internal registers on the low-to-high transition of
the clock (CLK) input when the appropriate
CLKEN
inputs are low. The select (SEL) line
selects 1B or 2B data for the A outputs. For data
transfer in the A-to-B direction, a two-stage
pipeline is provided in the A-to-1B path, with a
single storage register in the A-to-2B path.
Proper control of the CLKENA
inputs allows two sequential 12-bit words to be presented synchronously as a
24-bit word on the B port. Data flow is controlled by the active-low output enables (OEA
, OEB). The control
terminals are registered to synchronize the bus-direction changes with CLK.
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible and OE
should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver. Due to OE
being routed through a register, the active
state of the outputs cannot be determined prior to the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16270 is characterized for operation from –40°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
DGG OR DL PACKAGE
(TOP VIEW)
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OEA
CLKEN1B
2B3
GND
2B2
2B1
V
CC
A1
A2
A3
GND
A4
A5
A6
A7
A8
A9
GND
A10
A1 1
A12
V
CC
1B1
1B2
GND
1B3
CLKEN2B
SEL
OEB
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B1 1
2B12
1B12
1B1 1
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
SN74ALVCH16270
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES028F – JULY 1995 – REVISED FEBRUARY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
OUTPUT ENABLE
INPUTS
OUTPUTS
CLK OEA OEB A 1B, 2B
↑ H H Z Z
↑ HL ZActive
↑ L H Active Z
↑ L L Active Active
A-TO-B STORAGE (OEB = L)
INPUTS
OUTPUTS
CLKENA1 CLKENA2 CLK A 1B 2B
L H X X 1B
0
†
2B
0
†
L HXX1B
0
†
2B
0
†
L L ↑ LL
‡
L
L L ↑HH
‡
H
H L ↑ L1B
0
†
L
H L ↑ H1B
0
†
H
H H X X1B
0
†
2B
0
†
†
Output level before the indicated steady-state input
conditions were established
‡
Two CLK edges are needed to propagate data.
B-TO-A STORAGE (OEA
= L)
INPUTS
OUTPUT
CLKEN1B CLKEN2B CLK SEL 1B 2B
A
H X X H X X A
0
†
X HXLXXA
0
†
L X↑HLX L
L X ↑HHX H
X L ↑LXL L
X L ↑LXH H
†
Output level before the indicated steady-state input conditions were
established
SN74ALVCH16270
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES028F – JULY 1995 – REVISED FEBRUARY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
CLK
OEB
SEL
A1
1B1
2B1
CLKENA1
CLKENA2
1D
1D
CE
C1
1D
CE
C1
G1
1
1
1D
1D
CLKEN1B
C1
1D
1D
C1
CE
OEA
1D
C1
C1
CLKEN2B
1 of 12 Channels
CE
CE
C1
2
27
30
55
56
28
1
29
8
23
6
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