Texas Instruments SN74ALVCH16269DGGR, SN74ALVCH16269DL, SN74ALVCH16269DLR Datasheet
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic Shrink
Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
description
This 12-bit to 24-bit registered bus exchanger is
designed for 1.65-V to 3.6-V VCC operation.
The SN74AL VCH16269 is used in applications in
which two separate ports must be multiplexed
onto, or demultiplexed from, a single port. The
device is particularly suitable as an interface
between synchronous DRAMs and high-speed
microprocessors.
Data is stored in the internal B-port registers on
the low-to-high transition of the clock (CLK) input
when the appropriate clock-enable (CLKENA
inputs are low. Proper control of these inputs
allows two sequential 12-bit words to be
presented as a 24-bit word on the B port. For data
)
DGG OR DL PACKAGE
(TOP VIEW)
OEA
1
56
OEB2
OEB1
GND
GND
GND
GND
NC – No internal connection
2B3
2B2
2B1
V
CC
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
V
CC
1B1
1B2
1B3
NC
SEL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLKENA2
2B4
GND
2B5
2B6
V
CC
2B7
2B8
2B9
GND
2B10
2B11
2B12
1B12
1B11
1B10
GND
1B9
1B8
1B7
V
CC
1B6
1B5
GND
1B4
CLKENA1
CLK
transfer in the B-to-A direction, a single storage
register is provided. The select (SEL
) line selects 1B or 2B data for the A outputs. The register on the A output
permits the fastest possible data transfer, extending the period during which the data is valid on the bus. The
control terminals are registered so that all transactions are synchronous with CLK. Data flow is controlled by
the active-low output enables (OEA
, OEB1, OEB2).
To ensure the high-impedance state during power up or power down, a clock pulse should be applied as soon
as possible, and OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is
determined by the current-sinking capability of the driver. Due to OE being routed through a register , the active
state of the outputs cannot be determined before the arrival of the first clock pulse.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16269 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
Function Tables
OUTPUT ENABLE
INPUTS
CLK OEA OEB A 1B, 2B
↑ H H Z Z
↑ HL ZActive
↑ L H Active Z
↑ L L Active Active
OUTPUTS
A-TO-B STORAGE
INPUTS
CLKENA1 CLKENA2 CLK A 1B 2B
L H ↑ L L 2B
L H ↑ HH2B
L L ↑ LLL
L L ↑ HHH
H L ↑ L1B
H L ↑ H1B
H H X X 1B
†
Output level before the indicated steady-state input
conditions were established
B-TO-A STORAGE (OEA
INPUTS
CLK SEL 1B 2B
X H X X A
X LXX A
↑ HLX L
↑ HHX H
↑ LXL L
↑ L X H H
†
Output level before the indicated steady-state
input conditions were established
(OEB
= L)
= L)
OUTPUT
OUTPUTS
†
0
†
0
†
2B
0
A
†
0
†
0
†
0
†
0
L
H
†
0
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
29
CLK
2
OEB1
56
OEB2
SN74ALVCH16269
12-BIT TO 24-BIT REGISTERED BUS EXCHANGER
WITH 3-STATE OUTPUTS
SCES019I – JULY 1995 – REVISED SEPTEMBER 1999
C1
1D
C1
1D
CLKENA1
CLKENA2
SEL
OEA
A1
30
55
28
1
8
C1
1D
C1
1D
C1
1D
1 of 12 Channels
G1
1
1
CE
C1
1D
23
1B1
6
2B1
CE
C1
1D
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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