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SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode
D
B-Port Outputs Have Equivalent 26-Ω
Series Resistors, So No External Resistors
Are Required
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR.
description
This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V V
The SN74ALVCH162601 combines D-type
latches and D-type flip-flops to allow data flow in
transparent, latched, clocked, and clock-enabled
modes.
operation.
CC
DGG OR DL PACKAGE
(TOP VIEW)
OEAB
LEAB
GND
GND
GND
GND
OEBA
LEBA
A1
A2
A3
V
CC
A4
A5
A6
A7
A8
A9
A10
A1 1
A12
A13
A14
A15
V
CC
A16
A17
A18
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
CLKENAB
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B1 1
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
CLKENBA
Data flow in each direction is controlled by output-enable (OEAB
and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB
CLKENBA
) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low , the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB
OEAB
is high, the outputs are in the high-impedance state.
Data flow for B to A is similar to that of A to B, but uses OEBA
, LEBA, CLKBA, and CLKENBA.
is low, the outputs are active. When
The B-port outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus, EPIC, and UBT are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
and
1
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
description (continued)
The SN74ALVCH162601 is characterized for operation from –40°C to 85°C.
CLKAB
†
OUTPUT
A
B
‡
0
‡
0
‡
0
FUNCTION TABLE
INPUTS
CLKENAB OEAB
X H X X X Z
X LH XL L
X LH XH H
H LL XXB
H LL XXB
L LL ↑LL
L LL ↑HH
L LLL or H X B
†
A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA
LEBA, CLKBA, and CLKENBA
‡
Output level before the indicated steady-state input conditions were
established
LEAB
.
,
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
OEAB
CLKENAB
CLKAB
LEAB
LEBA
CLKBA
CLKENBA
OEBA
A1
1
56
55
2
28
30
29
27
3
CLK
CE
1D
C1
CE
1D
C1
CLK
54
B1
To 17 Other Channels
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I/O ports (see Notes 1 and 2) –0.5 V to V
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
CC
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
High-level output current (A port)
I
mA
High-level output current (B port)
Low-level output current (A port)
I
mA
Low-level output current (B port)
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
OH
OL
∆t/∆v Input transition rise or fall rate 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
p
p
p
p
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V 0.7
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –4
VCC = 2.3 V –12
VCC = 2.7 V –12
VCC = 3 V –24
VCC = 1.65 V –2
VCC = 2.3 V –6
VCC = 2.7 V –8
VCC = 3 V –12
VCC = 1.65 V 4
VCC = 2.3 V 12
VCC = 2.7 V 12
VCC = 3 V 24
VCC = 1.65 V 2
VCC = 2.3 V 6
VCC = 2.7 V 8
VCC = 3 V 12
CC
1.7
CC
CC
V
CC
V
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ALVCH162601
V
V
I
mA
A port
I
mA
I
mA
1.65 V
2.3 V
()
3 V
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
IOH = –6 mA 2.3 V 2
A port
IOH = –12 mA
OH
B port
p
V
OL
B port
I
I
I
I(hold)
§
I
OZ
I
CC
∆I
CC
C
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
§
For I/O ports, the parameter IOZ includes the input leakage current.
Control inputs VI = VCC or GND 3.3 V 4 pF
i
A or B ports VO = VCC or GND 3.3 V 8 pF
io
IOH = –24 mA 3 V 2
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –2 mA 1.65 V 1.2
IOH = –4 mA 2.3 V 1.9
= –6
OH
IOH = –8 mA 2.7 V 2
IOH = –12 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 4 mA 1.65 V 0.45
IOL = 6 mA 2.3 V 0.4
= 12
OL
IOL = 24 mA 3 V 0.55
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 2 mA 1.65 V 0.45
IOL = 4 mA 2.3 V 0.4
= 6
OL
IOL = 8 mA 2.7 V 0.6
IOL = 12 mA 3 V 0.8
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V
VI = 1.07 V
VI = 0.7 V
VI = 1.7 V
VI = 0.8 V
VI = 2 V
VI = 0 to 3.6 V
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
‡
V
CC
2.3 V 1.7
2.7 V 2.2
3 V 2.4
2.3 V 1.7
3 V 2.4
2.3 V 0.7
2.7 V 0.4
2.3 V 0.55
3 V 0.55
3.6 V ±500
MIN TYP†MAX UNIT
25
–25
45
–45
75
–75
V
µA
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
t
ns
tsuSetup time
Data before LE↓
ns
thHold time
Data after LE↓
ns
(INPUT)
(OUTPUT)
t
ns
PARAMETER
TEST CONDITIONS
UNIT
C
C
pF
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
f
clock
w
†
This information was not available at the time of publication.
Clock frequency
Pulse
duration
p
LE high
CLK high or low
Data before CLK↑
CLK high
CLK low
CLKEN before CLK↑
Data after CLK↑
CLK high
CLK low
CLKEN after CLK↑
VCC = 1.8 V
MIN MAX MIN MAX MIN MAX MIN MAX
†
†
†
†
†
†
†
†
†
†
VCC = 2.5 V
± 0.2 V
†
3.3 3.3 3.3
3.3 3.3 3.3
2.3 2.4 2.1
2 1.6 1.6
1.3 1.2 1.1
2 2 1.7
0.7 0.7 0.8
1.3 1.6 1.4
1.7 2 1.7
0.3 0.5 0.6
VCC = 2.7 V
140 150 150 MHz
VCC = 3.3 V
± 0.3 V
UNIT
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
f
max
pd
t
en
t
dis
t
en
t
dis
†
This information was not available at the time of publication.
FROM
A B
B A
LEAB B
LEBA A
CLKAB B
CLKBA A
OEAB
OEAB
OEBA
OEBA
TO
B
B
A
A
VCC = 1.8 V
MIN TYP MIN MAX MIN MAX MIN MAX
†
VCC = 2.5 V
± 0.2 V
140 150 150 MHz
†
1.3 4.8 5.2 1.6 4.5
†
†
†
†
†
†
†
†
†
1 4.3 4.6 1 4.1
1 5.5 5.9 1.5 5.1
1 5 5.3 1 4.7
1.5 6.1 6.3 1.6 5.5
1.3 5.6 5.8 1.4 5
1.6 6.1 6.7 1.6 5.7 ns
1.8 5.7 5.3 1.8 4.8 ns
1.1 5.5 6.1 1.1 5.2 ns
1.3 5.2 4.8 1.6 4.4 ns
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
operating characteristics, TA = 25°C
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
Power dissipation
pd
capacitance
†
This information was not available at the time of publication.
Outputs enabled
Outputs disabled
p
= 50 pF,f = 10 MHz
L
†
†
41 50
6 6
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
1 kΩ
1 kΩ
S1
V
2 × V
Open
GND
= 1.8 V
CC
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
18-BIT UNIVERSAL BUS TRANSCEIVER
SCES026G – JULY 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
500 Ω
500 Ω
S1
SN74ALVCH162601
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES026G – JULY 1995 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
S1
t
PHL
6 V
GND
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
V
Open
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
w
1.5 V
1.5 V
Open
6 V
GND
1.5 V1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 3. Load Circuit and Voltage Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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