TEXAS INSTRUMENTS SN74ALVCH162601 Technical data

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SN74ALVCH162601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES026G – JULY 1995 – REVISED JUNE 1999

D

Member of the Texas Instruments

D

Widebus
EPIC

 Family

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

UBT

 (Universal Bus Transceiver)

Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, Clocked, or Clock-Enabled Mode

D

B-Port Outputs Have Equivalent 26-Ω
Series Resistors, So No External Resistors
Are Required

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors

D

Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages

NOTE: For tape and reel order entry:

The DGGR package is abbreviated to GR.

description

This 18-bit universal bus transceiver is designed
for 1.65-V to 3.6-V V

The SN74ALVCH162601 combines D-type
latches and D-type flip-flops to allow data flow in
transparent, latched, clocked, and clock-enabled
modes.

operation.

CC

DGG OR DL PACKAGE

(TOP VIEW)

OEAB

LEAB

GND

GND

GND

GND

OEBA

LEBA

A1

A2
A3

V

CC

A4
A5
A6

A7
A8
A9

A10

A1 1

A12

A13
A14
A15

V

CC

A16
A17

A18

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

CLKENAB
CLKAB
B1
GND
B2
B3
V

CC

B4
B5
B6
GND
B7
B8
B9
B10
B1 1
B12
GND
B13
B14
B15
V

CC

B16
B17
GND
B18
CLKBA
CLKENBA

Data flow in each direction is controlled by output-enable (OEAB

and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. The clock can be controlled by the clock-enable (CLKENAB
CLKENBA

) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When
LEAB is low , the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A data is stored
in the latch/flip-flop on the low-to-high transition of CLKAB. When OEAB
OEAB

is high, the outputs are in the high-impedance state.

Data flow for B to A is similar to that of A to B, but uses OEBA

, LEBA, CLKBA, and CLKENBA.

is low, the outputs are active. When

The B-port outputs include equivalent 26-Ω series resistors to reduce overshoot and undershoot.
T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Widebus, EPIC, and UBT are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

and

1

SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES026G – JULY 1995 – REVISED JUNE 1999

description (continued)

The SN74ALVCH162601 is characterized for operation from –40°C to 85°C.

CLKAB

†

OUTPUT

A

B

‡

0

‡

0

‡

0

FUNCTION TABLE

INPUTS

CLKENAB OEAB

X H X X X Z
X LH XL L
X LH XH H
H LL XXB
H LL XXB
L LL ↑LL
L LL ↑HH
L LLL or H X B

†

A-to-B data flow is shown: B-to-A flow is similar, but uses OEBA
LEBA, CLKBA, and CLKENBA

‡

Output level before the indicated steady-state input conditions were
established

LEAB

.

,

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

SN74ALVCH162601

18-BIT UNIVERSAL BUS TRANSCEIVER

WITH 3-STATE OUTPUTS

SCES026G – JULY 1995 – REVISED JUNE 1999

OEAB

CLKENAB

CLKAB

LEAB

LEBA

CLKBA

CLKENBA

OEBA

A1

1

56

55

2

28

30

29

27

3

CLK

CE

1D
C1

CE
1D
C1

CLK

54

B1

To 17 Other Channels

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74ALVCH162601
18-BIT UNIVERSAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS

SCES026G – JULY 1995 – REVISED JUNE 1999

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V

Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

: Except I/O ports (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

I/O ports (see Notes 1 and 2) –0.5 V to V

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

JA

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

CC

+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . .

†

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265