Datasheet SN74ALVCH16244DGGR, SN74ALVCH16244DGVR, SN74ALVCH16244DL, SN74ALVCH16244DLR Datasheet (Texas Instruments)

SN74AL VCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES014E – JULY 1995 – REVISED FEBRUAR Y 1999
D
Member of the Texas Instruments
D
Widebus EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per JESD 17
D
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
D
Package Options Include Plastic 300-mil Shrink Small-Outline (DL), Thin Shrink Small-Outline (DGG), and Thin Very Small-Outline (DGV) Packages
description
This 16-bit buffer/driver is designed for 1.65-V to
3.6-V V The SN74ALVCH16244 is designed specifically
to improve the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
The device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. It provides true outputs and symmetrical active-low output-enable (OE
operation.
CC
) inputs.
DGG, DGV, OR DL PACKAGE
1OE
1Y1 1Y2
GND
1Y3 1Y4
V
CC
2Y1 2Y2
GND
2Y3 2Y4 3Y1 3Y2
GND
3Y3 3Y4
V
CC
4Y1 4Y2
GND
4Y3 4Y4
4OE
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
2OE 1A1 1A2 GND 1A3 1A4 V
CC
2A1 2A2 GND 2A3 2A4 3A1 3A2 GND 3A3 3A4 V
CC
4A1 4A2 GND 4A3 4A4 3OE
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. The SN74ALVCH16244 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 4-bit buffer)
INPUTS
OE A
L H H L LL
HXZ
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
OUTPUT
Y
Copyright 1999, Texas Instruments Incorporated
1
SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES014E – JULY 1995 – REVISED FEBRUAR Y 1999
logic symbol
1A1 1A2 1A3 1A4 2A1 2A2 2A3 2A4 3A1 3A2 3A3 3A4 4A1 4A2 4A3 4A4
1 48 25 24
47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
EN1 EN2 EN3 EN4
11 12 13 14 16 17 19 20 22 23
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2 2Y3 2Y4 3Y1 3Y2 3Y3 3Y4 4Y1 4Y2 4Y3 4Y4
1
1
1
2
1
3
1
4
1OE 2OE
3OE 4OE
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
logic diagram (positive logic)
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES014E – JULY 1995 – REVISED FEBRUAR Y 1999
1OE
1A1
1A2
1A3
1A4
2OE
2A1
2A2
2A3
2A4
1
47
46
44
43
48
41
40
38
37
11
12
25
3OE
2
1Y1
3
1Y2
5
1Y3
6
1Y4
8
2Y1
9
2Y2
2Y3
2Y4
3A1
3A2
3A3
3A4
4OE
4A1
4A2
4A3
4A4
36
35
33
32
24
30
29
27
26
13
14
16
17
19
20
22
23
3Y1
3Y2
3Y3
3Y4
4Y1
4Y2
4Y3
4Y4
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V Input voltage range, V Output voltage range, V Input clamp current, I Output clamp current, I Continuous output current, I Continuous current through each V Package thermal impedance, θ
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
3
SN74ALVCH16244
IOHHigh-level output current
mA
IOLLow-level output current
mA
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES014E – JULY 1995 – REVISED FEBRUAR Y 1999
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V V
t/v Input transition rise or fall rate 10 ns/V T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 2 VCC = 1.65 V to 1.95 V 0.35 × V VCC = 2.3 V to 2.7 V VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –4 VCC = 2.3 V –12 VCC = 2.7 V –12 VCC = 3 V –24 VCC = 1.65 V 4 VCC = 2.3 V 12 VCC = 2.7 V 12 VCC = 3 V 24
CC
1.7
0.7
CC CC
V
CC
V
V V
4
V
V
I
mA
()
C
V
V
GND
3.3 V
pF
(INPUT)
(OUTPUT)
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
SCES014E – JULY 1995 – REVISED FEBRUAR Y 1999
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2 IOH = –4 mA 1.65 V 1.2 IOH = –6 mA 2.3 V 2
V
OH
IOH = –12 mA
IOH = –24 mA 3 V 2 IOL = 100 µA 1.65 V to 3.6 V 0.2 IOL = 4 mA 1.65 V 0.45
OL
I
I
I
I(hold)
I
OZ
I
CC
I
CC
Control inputs
i
Data inputs
C
All typical values are at VCC = 3.3 V, TA = 25°C.
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
Outputs VO = VCC or GND 3.3 V 7 pF
o
IOL = 6 mA 2.3 V 0.4
= 12
OL
IOL = 24 mA 3 V 0.55 VI = VCC or GND 3.6 V ±5 µA VI = 0.58 V 1.65 V 25 VI = 1.07 V 1.65 V –25 VI = 0.7 V 2.3 V 45 VI = 1.7 V 2.3 V –45 VI = 0.8 V 3 V 75 VI = 2 V 3 V –75
CC
or
VI = 0 to 3.6 V VO = VCC or GND 3.6 V ±10 µA VI = VCC or GND, IO = 0 3.6 V 40 µA One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
=
I
V
CC
2.3 V 1.7
2.7 V 2.2 3 V 2.4
2.3 V 0.7
2.7 V 0.4
3.6 V ±500
MIN TYP†MAX UNIT
3 6
V
µA
p
switching characteristics over recommended operating free-air temperature range (unless otherwise noted) (see Figures 1 through 3)
PARAMETER
t
pd
t
en
t
dis
§
This information was not available at the time of publication.
FROM
A Y OE OE
TO
Y Y
VCC = 1.8 V
TYP MIN MAX MIN MAX MIN MAX
§
§
§
VCC = 2.5 V
± 0.2 V
1 3.7 3.6 1 3 ns 1 5.7 5.4 1 4.4 ns 1 5.2 4.6 1 4.1 ns
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
UNIT
5
SN74ALVCH16244
PARAMETER
TEST CONDITIONS
UNIT
C
C
pF
16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES014E – JULY 1995 – REVISED FEBRUAR Y 1999
operating characteristics, T
Power dissipation
pd
capacitance
This information was not available at the time of publication.
= 25°C
A
Outputs enabled Outputs disabled
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
Timing
Input
Data
Input
Input
Output
LOAD CIRCUIT
t
su
VCC/2
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
t
PLH
VCC/2 VCC/2
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
1 k
VCC/2
t
1 k
h
S1
VCC/2
p
= 50 pF,f = 10 MHz
L
= 1.8 V
V
CC
2 × V
CC
Open
GND
V
CC
0 V
V
CC
0 V
V
CC
S1 at 2 × V
0 V
t
PHL
V
OH
V
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
(see Note B)
Waveform 2
(see Note B)
CC
Output
S1 at GND
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
† †
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
VOLTAGE WA VEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
16 19
4 5
Open
2 × V
GND
t
w
VCC/2
VCC/2
CC
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
V
0 V
V
0 V
V
V
V
0 V
p
CC
CC
CC
OL
OH
NOTES: A. CL includes probe and jig capacitance.
6
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR10 MHz, ZO = 50 , tr≤2 ns, tf≤2 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
F. t
G. t
PLZ PZL PLH
and t and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
From Output
Under Test
CL = 30 pF
(see Note A)
SCES014E – JULY 1995 – REVISED FEBRUAR Y 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.5 V ± 0.2 V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
500
500
S1
SN74ALVCH16244
16-BIT BUFFER/DRIVER
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR10 MHz, ZO = 50 , tr≤2 ns, tf≤2 ns. D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WA VEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
7
SN74ALVCH16244 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS
SCES014E – JULY 1995 – REVISED FEBRUAR Y 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
Output
LOAD CIRCUIT
t
su
1.5 V 1.5 V
VOLTAGE WA VEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
VOLTAGE WA VEFORMS
PROPAGATION DELAY TIMES
500
500
1.5 V
t
h
t
PLH
1.5 V 1.5 V
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
S1
t
PHL
Open
GND
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
V
OH
OL
(see Note B)
(see Note B)
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
Output
Waveform 2
S1 at GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WA VEFORMS
PULSE DURATION
1.5 V 1.5 V
t
PZL
t
PZH
VOLTAGE WA VEFORMS
ENABLE AND DISABLE TIMES
t
w
1.5 V
1.5 V
Open
6 V
GND
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRRv10 MHz, ZO = 50 , trv D. The outputs are measured one at a time with one transition per measurement. E. t
F. t
G. t
PLZ PZL PLH
and t and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
Figure 3. Load Circuit and Voltage Waveforms
8
2.5 ns, tfv
.
2.5 ns.
IMPORTANT NOTICE
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Copyright 1999, Texas Instruments Incorporated
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