TEXAS INSTRUMENTS SN74ALVCH162373 Technical data

www.ti.com

DGG OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

1OE

1Q1
1Q2

GND

1Q3
1Q4
V

CC

1Q5
1Q6

GND

1Q7
1Q8
2Q1
2Q2

GND

2Q3
2Q4
V

CC

2Q5
2Q6

GND

2Q7
2Q8

2OE

1LE
1D1
1D2
GND
1D3
1D4
V

CC

1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V

CC

2D5
2D6
GND
2D7
2D8
2LE

查询SN74ALVCH162373供应商

FEATURES

• Member of the Texas Instruments Widebus™

Family

• Bus Hold on Data Inputs Eliminates the Need

for External Pullup/Pulldown Resistors

• Output Ports Have Equivalent 26- Ω Series

Resistors, So No External Resistors Are
Required

• Latch-Up Performance Exceeds 250 mA Per

JESD 17

• ESD Protection Exceeds JESD 22

– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)

DESCRIPTION/ORDERING INFORMATION

This 16-bit transparent D-type latch is designed for

1.65-V to 3.6-V V
The SN74ALVCH162373 is particularly suitable for

implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. This device can
be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels set up at
the D inputs.

A buffered output-enable ( OE) input can be used to
place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and the increased drive provide
the capability to drive bus lines without need for
interface or pullup components. OE does not affect
internal operations of the latch. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.

The outputs, which are designed to sink up to 12 mA, include equivalent 26- Ω resistors to reduce overshoot and
undershoot.

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at

www.ti.com/sc/package.

Widebus is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

16-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCES583A – JULY 2004 – REVISED OCTOBER 2004

operation.

CC

T

A

PACKAGE

-40 ° C to 85 ° C

SSOP - DL ALVCH162373

TSSOP - DGG Tape and reel SN74ALVCH162373GR ALVCH162373
VFBGA - GQL Tape and reel SN74ALVCH162373KR VH2373

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ORDERING INFORMATION

(1)

Tube SN74ALVCH162373DL
Tape and reel SN74ALVCH162373LR

ORDERABLE PART NUMBER TOP-SIDE MARKING

Copyright © 2004, Texas Instruments Incorporated

SN74ALVCH162373

www.ti.com

GQL PACKAGE

(TOP VIEW)

A
B
C
D
E

F
G
H

J
K

1 2 3 4 5 6

1OE

1LE

1D1

To Seven Other Channels

1Q1

2OE

2LE

2D1

2Q1

To Seven Other Channels

1

48

47

24

25

36

C1
1D

132

C1
1D

Pin numbers shown are for the DGG and DL packages.

SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS

SCES583A – JULY 2004 – REVISED OCTOBER 2004

DESCRIPTION/ORDERING INFORMATION (CONTINUED)

To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.

XXX

XXX

TERMINAL ASSIGNMENTS

1 2 3 4 5 6

A 1 OE NC NC NC NC 1LE
B 1Q2 1Q1 GND GND 1D1 1D2
C 1Q4 1Q3 V
D 1Q6 1Q5 GND GND 1D5 1D6
E 1Q8 1Q7 1D7 1D8
F 2Q1 2Q2 2D2 2D1
G 2Q3 2Q4 GND GND 2D4 2D3
H 2Q5 2Q6 V
J 2Q7 2Q8 GND GND 2D8 2D7
K 2 OE NC NC NC NC 2LE

V

CC

CC

CC

V

CC

through a pullup

CC

(1)

1D3 1D4

2D6 2D5

FUNCTION TABLE

(each 8-bit section)

INPUTS

OE LE D

L H H H
L H L L
L L X Q

H X X Z

LOGIC DIAGRAM (POSITIVE LOGIC)

(1) NC - No internal connection

OUTPUT

Q

0

2

www.ti.com

SN74ALVCH162373

16-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCES583A – JULY 2004 – REVISED OCTOBER 2004

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

V
V
V
I
I
I

θ

T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.

Supply voltage range -0.5 4.6 V

CC

Input voltage range

I

Output voltage range

O

Input clamp current VI< 0 -50 mA

IK

Output clamp current VO< 0 -50 mA

OK

Continuous output current ± 50 mA

O

(2)

(2) (3)

Continuous current through each V

Package thermal impedance

JA

Storage temperature range -65 150 ° C

stg

(4)

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(1)

MIN MAX UNIT

-0.5 4.6 V

-0.5 V

CC

or GND ± 100 mA

CC

DGG package 70
DL package 63 ° C/W
GQL package 42

+ 0.5 V

RECOMMENDED OPERATING CONDITIONS

(1)

MIN MAX UNIT

V

V

V

V

I

I

Supply voltage 1.65 3.6 V

CC

V

= 1.65 V to 1.95 V 0.65 × V

CC

High-level input voltage V

IH

Low-level input voltage V

IL

Output voltage 0 V

O

High-level output current mA

OH

Low-level output current mA

OL

= 2.3 V to 2.7 V 1.7 V

CC

V

= 2.7 V to 3.6 V 2 V

CC

V

= 1.65 V to 1.95 V 0 0.35 × V

CC

= 2.3 V to 2.7 V 0 0.7 V

CC

V

= 2.7 V to 3.6 V 0 0.8

CC

V

= 1.65 V -2

CC

V

= 2.3 V -6

CC

V

= 2.7 V -8

CC

V

= 3 V -12

CC

V

= 1.65 V 2

CC

V

= 2.3 V 6

CC

V

= 2.7 V 8

CC

V

= 3 V 12

CC

CC

∆ t/ ∆ v Input transition rise or fall rate 10 ns/V
T

(1) All unused control inputs of the device must be held at V

Operating free-air temperature -40 85 ° C

A

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

V

CC

V

CC
CC
CC

V

CC

3

www.ti.com

SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS

SCES583A – JULY 2004 – REVISED OCTOBER 2004

ELECTRICAL CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS V

IOH= -100 µ A 1.65 V to 3.6 V V

CC

MIN TYP

- 0.2

CC

IOH= -2 mA 1.65 V 1.2
IOH= -4 mA 2.3 V 1.9

V

OH

IOH= -6 mA

2.3 V 1.7 V
3 V 2.4

IOH= -8 mA 2.7 V 2
IOH= -12 mA 3 V 2
IOL= 100 µ A 1.65 V to 3.6 V 0.2
IOL= 2 mA 1.65 V 0.45
IOL= 4 mA 2.3 V 0.4

V

OL

IOL= 6 mA

2.3 V 0.55 V
3 V 0.55

IOL= 8 mA 2.7 V 0.6
IOL= 12 mA 3 V 0.8

I

I

VI= V

or GND 3.6 V ± 5 µ A

CC

VI= 0.58 V 1.65 V 25
VI= 1.07 V 1.65 V -25
VI= 0.7 V 2.3 V 45

I

I(hold)

VI= 1.7 V 2.3 V -45 µ A
VI= 0.8 V 3 V 75
VI= 2 V 3 V -75
VI= 0 to 3.6 V

I

OZ

I

CC

∆ I

CC

Control inputs 3

C

i

Data inputs 6

C

Outputs VO= V

o

(1) All typical values are at V
(2) This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to

VO= V
VI= V

CC

One input at V

VI= V

CC

CC

(2)

or GND 3.6 V ± 10 µ A

CC

3.6 V ± 500

or GND, IO= 0 3.6 V 40 µ A

- 0.6 V, Other inputs at V

CC

or GND 3 V to 3.6 V 750 µ A

CC

or GND 3.3 V pF

or GND 3.3 V 7 pF

CC

= 3.3 V, TA= 25 ° C.

another.

(1)

MAX UNIT

TIMING REQUIREMENTS

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)

V

= 1.8 V V

CC

± 0.15 V ± 0.2 V ± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

t

Pulse duration, LE high or low 3.3 3.3 3.3 3.3 ns

w

t

Setup time, data before LE ↓ 1.1 1.1 1.1 1.1 ns

su

t

Hold time, data after LE ↓ 1.1 1.1 1.1 1.1 ns

h

4

= 2.5 V V

CC

V

= 2.7 V

CC

= 3.3 V

CC

UNIT

www.ti.com

SN74ALVCH162373

16-BIT TRANSPARENT D-TYPE LATCH

WITH 3-STATE OUTPUTS

SCES583A – JULY 2004 – REVISED OCTOBER 2004

SWITCHING CHARACTERISTICS

over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)

V

= 1.8 V V

PARAMETER UNIT

t

pd

t

en

t

dis

t

sk(o)

FROM TO

(INPUT) (OUTPUT)

D 1 6.3 1 5.3 1 4.5 1.1 4

LE 1 6.6 1 5.6 1 5 1 4.2
OE Q 1 7.2 1 6.5 1.5 6 1 5 ns
OE Q 1 6.5 1 5.6 1.5 5.5 1.4 4.5 ns

Q ns

CC

± 0.15 V ± 0.2 V ± 0.3 V

MIN MAX MIN MAX MIN MAX MIN MAX

1 0.5 0.5 0.5 ns

OPERATING CHARACTERISTICS

TA= 25 ° C

PARAMETER TEST CONDITIONS UNIT

C

Power dissipation capacitance CL= 50 pF, f = 10 MHz pF

pd

Outputs enabled 20 22 26
Outputs disabled 6 6.5 8

= 2.5 V V

CC

V

= 1.8 V V

CC

TYP TYP TYP

V

CC

CC

= 2.7 V

= 2.5 V V

= 3.3 V

CC

= 3.3 V

CC

5

www.ti.com

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

M

V

OH

V

OL

t

h

t

su

From Output

Under Test

C

L

(see Note A)

LOAD CIRCUIT

S1

Open

GND

R

L

R

L

Output

Control

(low-level

enabling)

Output
Waveform 1
S1 at V

LOAD

(see Note B)

Output
Waveform 2

S1 at GND

(see Note B)

t

PZL

t

PZH

t

PLZ

t

PHZ

0 V

VOL + V

∆

VOH − V

∆

0 V

V

I

0 V

0 V

t

w

V

I

V

I

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Timing

Input

Data

Input

Input

t

pd

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

LOAD

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω.
D. The outputs are measured one at a time, with one transition per measurement.
E. t

PLZ

and t

PHZ

are the same as t

dis

.

F. t

PZL

and t

PZH

are the same as ten.

G. t

PLH

and t

PHL

are the same as tpd.

H. All parameters and waveforms are not applicable to all devices.

0 V

V

I

V

M

t

PHL

V

M

V

M

V

I

0 V

V

OH

V

OL

Input

Output

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

V

M

V

M

t

PLH

V

LOAD

V

LOAD

/2

1.8 V

2.5 V ± 0.2 V

2.7 V

3.3 V ± 0.3 V

1 kΩ
500 Ω
500 Ω
500 Ω

V

CC

R

L

2 × V

CC

2 × V

CC

6 V
6 V

V

LOAD

C

L

30 pF
30 pF
50 pF
50 pF

0.15 V

0.15 V

0.3 V

0.3 V

V

∆

V

CC

V

CC

2.7 V

2.7 V

V

I

VCC/2
VCC/2

1.5 V

1.5 V

V

M

tr/t

f

≤2 ns

≤2 ns
≤2.5 ns
≤2.5 ns

INPUT

SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS

SCES583A – JULY 2004 – REVISED OCTOBER 2004

PARAMETER MEASUREMENT INFORMATION

Figure 1. Load Circuit and Voltage Waveforms

6

MECHANICAL DATA

MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001

DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0.025 (0,635)

48

1

0.110 (2,79) MAX

0.0135 (0,343)

0.008 (0,203)
25

0.299 (7,59)

0.291 (7,39)

24

A

0.008 (0,20) MIN

0.005 (0,13)

0.420 (10,67)

0.395 (10,03)

Seating Plane

0.004 (0,10)

M

0.010 (0,25)

0.005 (0,13)

Gage Plane

0.010 (0,25)

0°–ā8°

0.040 (1,02)

0.020 (0,51)

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118

0.380

(9,65)

0.370

(9,40)

4828

0.630

(16,00)

0.620

(15,75)

56

0.730

(18,54)

0.720

(18,29)

4040048/E 12/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS003D – JANUARY 1995 – REVISED JANUARY 1998

DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

48 PINS SHOWN

0,50

48

1

1,20 MAX

0,27
0,17

25

24

A

0,15
0,05

0,08

M

6,20

8,30

6,00

7,90

Seating Plane

0,10

0,15 NOM

Gage Plane

0,25

0°–8°

0,75
0,50

DIM

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153

PINS **

A MAX

A MIN

48

12,60

12,40

56

14,10

13,90

64

17,10

16,90

4040078/F 12/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,
enhancements, improvements, and other changes to its products and services at any time and to discontinue
any product or service without notice. Customers should obtain the latest relevant information before placing
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms
and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI
deems necessary to support this warranty . Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.

TI assumes no liability for applications assistance or customer product design. Customers are responsible for
their products and applications using TI components. To minimize the risks associated with customer products
and applications, customers should provide adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,
copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process
in which TI products or services are used. Information published by TI regarding third-party products or services
does not constitute a license from TI to use such products or services or a warranty or endorsement thereof.
Use of such information may require a license from a third party under the patents or other intellectual property
of the third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of information in TI data books or data sheets is permissible only if reproduction is without
alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction
of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for
such altered documentation.

Resale of TI products or services with statements different from or beyond the parameters stated by TI for that
product or service voids all express and any implied warranties for the associated TI product or service and
is an unfair and deceptive business practice. TI is not responsible or liable for any such statements.

Following are URLs where you can obtain information on other Texas Instruments products and application
solutions:

Products Applications

Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive

DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless

Mailing Address: Texas Instruments

Post Office Box 655303 Dallas, Texas 75265

Copyright  2004, Texas Instruments Incorporated