TEXAS INSTRUMENTS SN74ALVCH162373 Technical data
www.ti.com
DGG OR DL PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
查询SN74ALVCH162373供应商
FEATURES
• Member of the Texas Instruments Widebus™
Family
• Bus Hold on Data Inputs Eliminates the Need
for External Pullup/Pulldown Resistors
• Output Ports Have Equivalent 26- Ω Series
Resistors, So No External Resistors Are
Required
• Latch-Up Performance Exceeds 250 mA Per
JESD 17
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
DESCRIPTION/ORDERING INFORMATION
This 16-bit transparent D-type latch is designed for
1.65-V to 3.6-V V
The SN74ALVCH162373 is particularly suitable for
implementing buffer registers, I/O ports, bidirectional
bus drivers, and working registers. This device can
be used as two 8-bit latches or one 16-bit latch.
When the latch-enable (LE) input is high, the Q
outputs follow the data (D) inputs. When LE is taken
low, the Q outputs are latched at the levels set up at
the D inputs.
A buffered output-enable ( OE) input can be used to
place the eight outputs in either a normal logic state
(high or low logic levels) or the high-impedance state.
In the high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and the increased drive provide
the capability to drive bus lines without need for
interface or pullup components. OE does not affect
internal operations of the latch. Old data can be
retained or new data can be entered while the
outputs are in the high-impedance state.
The outputs, which are designed to sink up to 12 mA, include equivalent 26- Ω resistors to reduce overshoot and
undershoot.
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Widebus is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES583A – JULY 2004 – REVISED OCTOBER 2004
operation.
CC
T
A
PACKAGE
-40 ° C to 85 ° C
SSOP - DL ALVCH162373
TSSOP - DGG Tape and reel SN74ALVCH162373GR ALVCH162373
VFBGA - GQL Tape and reel SN74ALVCH162373KR VH2373
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
ORDERING INFORMATION
(1)
Tube SN74ALVCH162373DL
Tape and reel SN74ALVCH162373LR
ORDERABLE PART NUMBER TOP-SIDE MARKING
Copyright © 2004, Texas Instruments Incorporated
SN74ALVCH162373
www.ti.com
GQL PACKAGE
(TOP VIEW)
A
B
C
D
E
F
G
H
J
K
1 2 3 4 5 6
1OE
1LE
1D1
To Seven Other Channels
1Q1
2OE
2LE
2D1
2Q1
To Seven Other Channels
1
48
47
24
25
36
C1
1D
132
C1
1D
Pin numbers shown are for the DGG and DL packages.
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES583A – JULY 2004 – REVISED OCTOBER 2004
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE should be tied to V
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown
resistors with the bus-hold circuitry is not recommended.
XXX
XXX
TERMINAL ASSIGNMENTS
1 2 3 4 5 6
A 1 OE NC NC NC NC 1LE
B 1Q2 1Q1 GND GND 1D1 1D2
C 1Q4 1Q3 V
D 1Q6 1Q5 GND GND 1D5 1D6
E 1Q8 1Q7 1D7 1D8
F 2Q1 2Q2 2D2 2D1
G 2Q3 2Q4 GND GND 2D4 2D3
H 2Q5 2Q6 V
J 2Q7 2Q8 GND GND 2D8 2D7
K 2 OE NC NC NC NC 2LE
V
CC
CC
CC
V
CC
through a pullup
CC
(1)
1D3 1D4
2D6 2D5
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE LE D
L H H H
L H L L
L L X Q
H X X Z
LOGIC DIAGRAM (POSITIVE LOGIC)
(1) NC - No internal connection
OUTPUT
Q
0
2
www.ti.com
SN74ALVCH162373
16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCES583A – JULY 2004 – REVISED OCTOBER 2004
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
V
V
V
I
I
I
θ
T
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 4.6 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
Supply voltage range -0.5 4.6 V
CC
Input voltage range
I
Output voltage range
O
Input clamp current VI< 0 -50 mA
IK
Output clamp current VO< 0 -50 mA
OK
Continuous output current ± 50 mA
O
(2)
(2) (3)
Continuous current through each V
Package thermal impedance
JA
Storage temperature range -65 150 ° C
stg
(4)
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(1)
MIN MAX UNIT
-0.5 4.6 V
-0.5 V
CC
or GND ± 100 mA
CC
DGG package 70
DL package 63 ° C/W
GQL package 42
+ 0.5 V
RECOMMENDED OPERATING CONDITIONS
(1)
MIN MAX UNIT
V
V
V
V
I
I
Supply voltage 1.65 3.6 V
CC
V
= 1.65 V to 1.95 V 0.65 × V
CC
High-level input voltage V
IH
Low-level input voltage V
IL
Output voltage 0 V
O
High-level output current mA
OH
Low-level output current mA
OL
= 2.3 V to 2.7 V 1.7 V
CC
V
= 2.7 V to 3.6 V 2 V
CC
V
= 1.65 V to 1.95 V 0 0.35 × V
CC
= 2.3 V to 2.7 V 0 0.7 V
CC
V
= 2.7 V to 3.6 V 0 0.8
CC
V
= 1.65 V -2
CC
V
= 2.3 V -6
CC
V
= 2.7 V -8
CC
V
= 3 V -12
CC
V
= 1.65 V 2
CC
V
= 2.3 V 6
CC
V
= 2.7 V 8
CC
V
= 3 V 12
CC
CC
∆ t/ ∆ v Input transition rise or fall rate 10 ns/V
T
(1) All unused control inputs of the device must be held at V
Operating free-air temperature -40 85 ° C
A
or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
V
CC
V
CC
CC
CC
V
CC
3
Loading...