SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D
Package Options Include Plastic 300-mil
Shrink Small-Outline (DGG), Thin Shrink
Small-Outline (DL), and Thin Very
Small-Outline (DGV) Packages
NOTE: For tape and reel order entry:
The DGGR package is abbreviated to GR, and
the DGVR package is abbreviated to VR.
description
This 1-bit to 4-bit address driver is designed for
1.65-V to 3.6-V V
The SN74ALVCH162344 is used in applications
in which four separate memory locations must be
addressed by a single address.
The outputs, which are designed to sink up to
12 mA, include equivalent 26-Ω resistors to
reduce overshoot and undershoot.
operation.
CC
DGG, DGV, OR DL PACKAGE
OE1
1B1
1B2
GND
1B3
1B4
V
CC
1A
2B1
2B2
GND
2B3
2B4
2A
3A
3B1
3B2
GND
3B3
3B4
4A
V
CC
4B1
4B2
GND
4B3
4B4
OE2
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE4
8B1
8B2
GND
8B3
8B4
V
CC
8A
7B1
7B2
GND
7B3
7B4
7A
6A
6B1
6B2
GND
6B3
6B4
5A
V
CC
5B1
5B2
GND
5B3
5B4
OE3
T o ensure the high-impedance state during power
up or power down, the output enable (OE) inputs
should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the
current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH162344 is characterized for operation from –40°C to 85°C.
A-TO-B FUNCTION TABLE
INPUTS
OE A
L H H
L LL
H X Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
OUTPUT
Bn
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
logic diagram (positive logic)
OE4
OE3
OE2
OE1
1A
2A
56
29
28
1
8
14
10
12
2
1B1
3
1B2
5
1B3
6
1B4
9
2B1
2B2
2B3
5A
6A
36
42
34
33
31
30
41
40
38
5B1
5B2
5B3
5B4
6B1
6B2
6B3
3A
4A
15
21
13
16
17
19
20
23
24
26
27
2B4
3B1
3B2
3B3
3B4
4B1
4B2
4B3
4B4
7A
8A
43
49
37
48
47
45
44
55
54
52
51
6B4
7B1
7B2
7B3
7B4
8B1
8B2
8B3
8B4
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IOHHigh-level output current
mA
IOLLow-level output current
mA
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
∆t/∆v Input transition rise or fall rate 10 ns/V
T
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –2
VCC = 2.3 V –6
VCC = 2.7 V –8
VCC = 3 V –12
VCC = 1.65 V 2
VCC = 2.3 V 6
VCC = 2.7 V 8
VCC = 3 V 12
CC
1.7
0.7
CC
CC
V
CC
V
V
V
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVCH162344
I
mA
I
mA
()
C
V
V
GND
3.3 V
pF
(INPUT)
(OUTPUT)
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –2 mA 1.65 V 1.2
IOH = –4 mA 2.3 V 1.9
V
OH
V
OL
I
I
I
I(hold)
I
OZ
I
CC
∆I
CC
Control inputs
i
Data inputs
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
‡
This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
Outputs VO = VCC or GND 3.3 V 4 pF
o
= –6
OH
IOH = –8 mA 2.7 V 2
IOH = –12 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 2 mA 1.65 V 0.45
IOL = 4 mA 2.3 V 0.4
= 6
OL
IOL = 8 mA 2.7 V 0.6
IOL = 12 mA 3 V 0.8
VI = VCC or GND 3.6 V ±5 µA
VI = 0.58 V 1.65 V 25
VI = 1.07 V 1.65 V –25
VI = 0.7 V 2.3 V 45
VI = 1.7 V 2.3 V –45
VI = 0.8 V 3 V 75
VI = 2 V 3 V –75
CC
‡
or
VI = 0 to 3.6 V
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
=
I
V
CC
2.3 V 1.7
3 V 2.4
2.3 V 0.55
3 V 0.55
3.6 V ±500
MIN TYP†MAX UNIT
2.5
3.5
V
V
µA
p
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
t
pd
t
en
t
dis
¶
t
sk(o)
#
t
sk(o)
§
This information was not available at the time of publication.
¶
Skew between outputs of the same bank and same package (same transition)
#
Skew between outputs of all banks of same package (A1–A8 tied together)
4
FROM
A B
OE
OE
TO
B
B
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VCC = 1.8 V
TYP MIN MAX MIN MAX MIN MAX
§
§
§
VCC = 2.5 V
± 0.2 V
1 4.9 5.1 1.4 4.4 ns
1 6.4 6.6 1.2 5.7 ns
1 5.4 4.7 1.2 4.5 ns
VCC = 2.7 V
VCC = 3.3 V
± 0.3 V
0.35 ns
0.5 ns
UNIT
PARAMETER
TEST CONDITIONS
UNIT
C
C
pF
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
operating characteristics, T
Power dissipation
pd
capacitance
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
Timing
Input
Data
Input
Input
t
Output
1 kΩ
LOAD CIRCUIT
t
su
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
PLH
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1 kΩ
VCC/2
t
h
S1
VCC/2
= 0,f = 10 MHz
L
V
CC
2 × V
CC
Open
GND
V
CC
0 V
V
CC
0 V
V
CC
0 V
t
PHL
V
OH
V
OL
= 1.8 V
Waveform 1
S1 at 2 × V
(see Note B)
Waveform 2
(see Note B)
Input
Output
Control
(low-level
enabling)
Output
CC
Output
S1 at GND
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
†
†
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
68 82
12 14
Open
2 × V
GND
t
w
VCC/2
VCC/2
CC
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
V
0 V
V
0 V
V
V
V
0 V
p
CC
CC
CC
OL
OH
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
= 2.5 V ± 0.2 V
V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
PLZ
F. t
PZL
G. t
PLH
VCC/2
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PHZ
and t
PZH
and t
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
Figure 2. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ALVCH162344
1-BIT TO 4-BIT ADDRESS DRIVER
WITH 3-STATE OUTPUTS
SCES085F – AUGUST 1996 – REVISED JUNE 1999
PARAMETER MEASUREMENT INFORMATION
= 2.7 V AND 3.3 V ± 0.3 V
V
CC
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
t
PLH
Output
500 Ω
500 Ω
LOAD CIRCUIT
1.5 V
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
h
1.5 V
S1
t
PHL
6 V
GND
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
V
Open
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Open
6 V
GND
t
w
1.5 V 1.5 V
1.5 V
1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
2.7 V
0 V
2.7 V
0 V
3 V
V
OL
V
OH
0 V
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
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