Texas Instruments SN74ALVC7805-25DL, SN74ALVC7805-40DL, SN74ALVC7805-20DL, SN74ALVC7805-20DLR Datasheet
SN74ALVC7805
256 × 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus Family
D
Low-Power Advanced CMOS Technology
D
Operates From 3-V to 3.6-V V
CC
D
Free-Running Read and Write Clocks Can
Be Asynchronous or Coincident
D
Read and Write Operations Synchronized
to Independent System Clocks
D
Half-Full Flag and Programmable
Almost-Full/Almost-Empty Flag
D
Bidirectional Configuration and Width
Expansion Without Additional Logic
D
Input-Ready Flag Synchronized to Write
Clock
D
Output-Ready Flag Synchronized to Read
Clock
D
Fast Access Times of 13 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
D
Data Rates up to 50 MHz
D
Pin-to-Pin Compatible With SN74ACT7803,
SN74ACT7805, and SN74ACT7813
D
Packaged in Shrink Small-Outline 300-mil
Package Using 25-mil Center-to-Center
Lead Spacing
description
The SN74ALVC7805 is suited for buffering
asynchronous data paths up to 50-MHz clock
rates and 13-ns access times. This device is
designed for 3-V to 3.6-V V
CC
operation. Two
devices can be configured for bidirectional data
buffering without additional logic.
The write clock (WRTCLK) and read clock (RDCLK) are free running and can be asynchronous or coincident.
Data is written to memory on the rising edge of WRTCLK when WRTEN1 is high, WRTEN2
is low, and input
ready (IR) is high. Data is read from memory on the rising edge of RDCLK when RDEN
, OE1, and OE2 are low
and output ready (OR) is high. The first word written to memory is clocked through to the output buffer,
regardless of the RDEN
, OE1, and OE2 levels. The OR flag indicates that valid data is present on the output
buffer.
The FIFO can be reset asynchronously to WRTCLK and RDCLK. Reset (RESET
) must be asserted while at
least four WRTCLK and four RDCLK rising edges occur to clear the synchronizing registers. Resetting the FIFO
initializes the IR, OR, and half-full (HF) flags low and the almost-full/almost-empty (AF/AE) flag high. The FIFO
must be reset upon power up.
The SN74ALVC7805 is characterized for operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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14
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19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
RESET
D17
D16
D15
D14
D13
D12
D11
D10
V
CC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
AF/AE
WRTCLK
WRTEN2
WRTEN1
IR
OE1
Q17
Q16
Q15
GND
Q14
V
CC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
CC
Q4
Q3
Q2
GND
Q1
Q0
RDCLK
RDEN
OE2
OR
DL PACKAGE
(TOP VIEW)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus is a trademark of Texas Instruments Incorporated.
SN74ALVC7805
256 × 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol
†
Almost-Full/Empty
FIFO 256 × 18
Φ
WRTEN
&
RDEN
&
0
21
D0
20
D1
19
D2
18
D3
17
D4
16
D5
15
D6
14
D7
12
D8
Q0
33
0
Q1
34
Q2
36
Q3
37
Q4
38
IR
28
Input Ready
HF
22
Half-Full
AF/AE
24
OR
29
Output Ready
Q5
40
Q6
41
Q7
42
Q8
43
Data
1
11
D9
9
D10
8
D11
7
D12
6
D13
5
D14
4
D15
3
D16
17
2
D17
Q9
45
Q10
46
Q11
47
Q12
48
Q13
49
Q14
51
Q15
53
Q16
54
Q17
55
17
RESET
WRTEN2
OE1
OE2
RDEN
30
EN1
&
56
PEN
RESET
1
25
WRTCLK
WRTCLK
Data
27
WRTEN1
26
Program Enable
23
31
32
RDCLK
RDCLK
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN74ALVC7805
256 × 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
Q0–Q17
IR
AF/AE
HF
Register
256 × 18
OE2
D0–D17
RDCLK
OE1
RDEN
WRTCLK
WRTEN1
WRTEN2
RESET
PEN
Synchronous
Read
Control
Synchronous
Write
Control
Reset
Logic
Read
Pointer
Write
Pointer
Status-
Flag
Logic
Output
Control
OR
RAM
SN74ALVC7805
256 × 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
AF/AE 24 O
Almost-full/almost-empty flag. Depth-offset values can be programmed for this flag, or the default
value of 32 can be used for both the almost-empty offset (X) and the almost-full offset (Y). AF/AE is
high when memory contains X or fewer words or (256 – Y) or more words. AF/AE is high after reset.
D0–D17
2–9, 11–12,
14–21
I 18-bit data input port
HF 22 O Half-full flag. HF is high when the FIFO memory contains 128 or more words. HF is low after reset.
IR 28 O
Input-ready flag. IR is synchronized to the low-to-high transition of WRTCLK. When IR is low , the FIFO
is full and writes are disabled. IR is low during reset and goes high on the second low-to-high transition
of WRTCLK after reset.
OE1
OE2
56
30
I
Output enables. When OE1, OE2, and RDEN are low and OR is high, data is read from the FIFO on
a low-to-high transition of RDCLK. When either OE1
or OE2 is high, reads are disabled and the data
outputs are in the high-impedance state.
OR 29 O
Output-ready flag. OR is synchronized to the low-to-high transition of RDCLK. When OR is low, the
FIFO is empty and reads are disabled. Ready data is present on Q0–Q17 when OR is high. OR is low
during reset and goes high on the third low-to-high transition of RDCLK after the first word is loaded
to empty memory.
PEN
23 I
Program enable. After reset and before the first word is written to the FIFO, the binary value on D0–D7
is latched as an AF/AE offset value when PEN
is low and WRTCLK is high.
Q0–Q17
33–34, 36–38,
40–43, 45–49,
51, 53–55
O
18-bit data output port. After the first valid write to empty memory, the first word is output on Q0–Q17
on the third rising edge of RDCLK. OR also is asserted high at this time to indicate ready data. When
OR is low, the last word read from the FIFO is present on Q0–Q17.
RDCLK 32 I
Read clock. RDCLK is a continuous clock and can be asynchronous or coincident to WRTCLK. A
low-to-high transition of RDCLK reads data from memory when OE1
, OE2, and RDEN are low and OR
is high. OR is synchronous to the low-to-high transition of RDCLK.
RDEN
31 I
Read enable. When RDEN, OE1, and OE2 are low and OR is high, data is read from the FIFO on the
low-to-high transition of RDCLK.
RESET
1 I
Reset. To reset the FIFO, four low-to-high transitions of RDCLK and four low-to-high transitions of
WRTCLK must occur while RESET
is low. This sets HF, IR, and OR low and AF/AE high.
WRTCLK 25 I
Write clock. WRTCLK is a continuous clock and can be asynchronous or coincident to RDCLK. A
low-to-high transition of WRTCLK writes data to memory when WRTEN2
is low, WRTEN1 is high, and
IR is high. IR is synchronous to the low-to-high transition of WRTCLK.
WRTEN1
WRTEN2
27
26
I
Write enables. When WRTEN1 is high, WRTEN2 is low, and IR is high, data is written to the FIFO on
a low-to-high transition of WRTCLK.
SN74ALVC7805
256 × 18
LOW-POWER CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCAS593A – OCTOBER 1997 – REVISED APRIL 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
123412
Don’t Care
Don’t Care
Don’t Care
1234
Don’t Care
Don’t Care
Don’t Care
Invalid
Don’t Care
Don’t Care
Don’t Care
Don’t Care
RESET
WRTCLK
PEN
WRTEN1
WRTEN2
D0–D17
RDCLK
OE1
OE2
RDEN
Q0–Q17
OR
AF/AE
HF
IR
Define the AF/AE Flag Using the Default Value of X = Y = 32
Figure 1. Reset Cycle
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