Texas Instruments SN74ALVC7804-25DL, SN74ALVC7804-40DL Datasheet
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMORY
SCAS432 – JANUARY 1995
D17
D16
D15
D14
D13
D12
D1 1
D10
V
CC
D9
D8
GND
D7
D6
D5
D4
D3
D2
D1
D0
HF
PEN
LDCK
NC
NC
FULL
DL PACKAGE
(TOP VIEW)
1
56
2
55
3
54
4
53
5
52
6
51
7
50
8
49
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
25
32
26
31
27
30
28
29
OE
Q17
Q16
Q15
GND
Q14
V
CC
Q13
Q12
Q11
Q10
Q9
GND
Q8
Q7
Q6
Q5
V
CC
Q4
Q3
Q2
GND
Q1
Q0
UNCK
NC
NC
EMPTY
• Operates at 3-V to 3.6-V V
CC
• Load Clock and Unload Clock Can Be
Asynchronous or Coincident
• Low-Power Advanced CMOS Technology
• Full, Empty, and Half-Full Flags
• Programmable Almost-Full/Almost-Empty
Flag
• Fast Access Times of 18 ns With a 50-pF
Load and All Data Outputs Switching
Simultaneously
• Data Rates From 0 to 40 MHz
• 3-State Outputs
• Pin Compatible With SN74ACT7804
• Packaged in Shrink Small-Outline 300-mil
Package (DL) Using 25-mil Center-to-Center
Spacing
description
A FIFO memory is a storage device that allows
data to be written into and read from its array at
independent data rates. The SN74ALVC7804 is
an 18-bit FIFO with high speed and fast access
times. Data is processed at rates up to 40 MHz
with access times of 18 ns in a bit-parallel format.
The SN74AL VC7804 is designed for 3-V to 3.6-V
V
operation.
CC
Data is written into memory on a low-to-high
transition of the load clock (LDCK) and is read out
on a low-to-high transition of the unload clock
RESET
AF/AE
(UNCK). The memory is full when the number of
words clocked in exceeds the number of words clocked out by 512. When the memory is full, LDCK has no effect
on the data residing in memory. When the memory is empty, UNCK has no effect.
Status of the FIFO memory is monitored by the full (FULL
full/almost-empty (AF/AE) flags. The FULL
is not full. The EMPTY
output is low when the memory is empty and high when it is not empty . The HF output
output is low when the memory is full and high when the memory
), empty (EMPTY), half-full (HF), and almost-
is high whenever the FIFO contains 256 or more words and is low when it contains 255 or less words. The AF/AE
status flag is a programmable flag. The first one or two low-to-high transitions of LDCK after reset are used to
program the almost-empty offset value (X) and the almost-full offset value (Y), if program enable (PEN
The AF/AE flag is high when the FIFO contains X or less words or (512 minus Y) or more words. The AF/AE
flag is low when the FIFO contains between (X plus 1) and (511 minus Y) words.
A low level on the reset (RESET
and EMPTY
low. The Q outputs are not reset to any specific logic level. The FIFO must be reset upon power
up. The first word loaded into empty memory causes EMPTY
The data outputs are in the high-impedance state when the output-enable (OE
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
) resets the internal stack pointers and sets FULL high, AF/AE high, HF low,
to go high and the data to appear on the Q outputs.
) is high.
Copyright 1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
) is low.
1
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMOR Y
SCAS432 – JANUARY 1995
logic symbol
†
Φ
FIFO 512 × 18
RESET
LDCK
UNCK
OE
PEN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
1
25
32
56
23
21
20
19
18
17
16
15
14
12
11
9
8
7
6
5
4
3
2
RESET
LDCK
UNCK
EN1
Program Enable
0
Data
17
Full
Half-Full
Almost Full/Empty
Empty
Data
1
17
28
FULL
22
HF
24
AF/AE
29
EMPTY
33
0
34
36
37
38
40
41
42
43
45
46
47
48
49
51
53
54
55
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
Q16
Q17
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
I/O
DESCRIPTION
OE
D0–D17
UNCK
Read
Pointer
SN74ALVC7804
512 × 18
FIRST-IN, FIRST-OUT MEMOR Y
SCAS432 – JANUARY 1995
RAM
512 × 18
LDCK
RESET
PEN
Write
Pointer
Reset
Logic
Status-
Flag
Logic
Q0–Q17
EMPTY
FULL
HF
AF/AE
Terminal Functions
TERMINAL
NAME NO.
Almost full/almost empty flag. Depth offset values can be programmed for AF/AE, or the default
AF/AE 24 O
D0–D17
EMPTY 29 O Empty flag. EMPTY is low when the FIFO is empty. A FIFO reset also causes EMPTY to go low.
FULL 28 O Full flag. FULL is low when the FIFO is full. A FIFO reset causes FULL to go high.
HF 22 O Half-full flag. HF is high when the FIFO memory contains 256 or more words. HF is low after reset.
LDCK 25 I Load clock. Data is written to the FIFO on the rising edge of LDCK when FULL is high.
OE 56 I Output enable. When OE is high, the data outputs are in the high-impedance state.
PEN 23 I
Q0–Q17
RESET 1 I
UNCK 32 I Unload clock. Data is read from the FIFO on the rising edge of UNCK when EMPTY is high.
21–14, 12–11,
9–2
33–34, 36–38,
40–43, 45–49,
51, 53–55
value of 64 can be used for both the almost empty offset (X) and the almost full offset (Y). AF/AE
is high when memory contains X or less words or (512 – Y) or more words. AF/AE is high after
reset.
I 18-bit data input port
Program enable. After reset and before the first word is written to the FIFO, the binary value on
D0–D7 is latched as an AF/AE offset value when PEN
O 18-bit data output port
Reset. A low level on RESET resets the FIFO and drives AF/AE and FULL high and HF and
low.
EMPTY
is low and WRTCLK is high.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
4
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ÉÉ
ÉÉ
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ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
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ÉÉ
ÉÉ
ÉÉ
ÉÉ
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ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
ÉÉ
SCAS432 – JANUARY 1995
FIRST-IN, FIRST-OUT MEMOR Y
SN74ALVC7804
512 × 18
RESET
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PEN
LDCK
D0–D17
UNCK
OE
Q0–Q17
EMPTY
AF/AE
W1 W2
(X+1)
1
0
W
A
B
C
Don’t Care
1
0
W
W1
W
W2 DE
(Y+1)
(Y+2)
H I
G F
HF
FULL
Define the AF/AE Flag
Using the Default Value of X and Y
Figure 1. Write, Read, and Flag Timing Reference
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