Datasheet SN74ALVC164245DGGR, SN74ALVC164245DL, SN74ALVC164245DLR Datasheet (Texas Instruments)

OPERATION
SN74ALVC164245
16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999
D
D
Widebus EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Latch-Up Performance Exceeds 250 mA Per JESD 17
D
Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages
description
This 16-bit (dual-octal) noninverting bus transceiver contains two separate supply rails; B port has V V
, which is set to operate at 3.3 V . This allows
CCA
for translation from a 3.3-V to a 5-V environment and vice versa.
The SN74ALVC164245 is designed for asynchronous communication between data buses.
T o ensure the high-impedance state during power up or power down, the output-enable (OE should be tied to V minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ALVC164245 is characterized for operation from –40°C to 85°C.
, which is set at 5 V , and A port has
CCB
through a pullup resistor; the
CC
) input
DGG OR DL PACKAGE
1DIR
1B1 1B2
GND
1B3 1B4
(5 V) V
CCB
1B5 1B6
GND
1B7 1B8 2B1 2B2
GND
2B3 2B4
(5 V) V
CCB
2B5 2B6
GND
2B7 2B8
2DIR
(TOP VIEW)
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17
32
18
31
19
30
20
29
21
28
22
27
23
26
24
25
1OE 1A1 1A2 GND 1A3 1A4 V
CCA
1A5 1A6 GND 1A7 1A8 2A1 2A2 GND 2A3 2A4 V
CCA
2A5 2A6 GND 2A7 2A8 2OE
(3.3 V)
(3.3 V)
FUNCTION TABLE
(each 8-bit section)
INPUTS
DIR
OE
L L B data to A bus L H A data to B bus
H X Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
Copyright 1999, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1
SN74ALVC164245 16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999
logic symbol
1OE
1DIR
2OE
2DIR
1A1
1A2 1A3 1A4 1A5 1A6 1A7 1A8 2A1
2A2 2A3 2A4 2A5 2A6 2A7 2A8
48 1
25 24
47
46 44 43 41 40 38 37 36
35 33 32 30 29 27 26
G3 3 EN1 [BA]
3 EN2 [AB] G6 6 EN4 [BA]
6 EN5 [AB]
1
4
2
1B1
2
5
11 12 13
14 16 17 19 20 22 23
3
1B2
5
1B3
6
1B4
8
1B5
9
1B6 1B7 1B8 2B1
2B2 2B3 2B4 2B5 2B6 2B7 2B8
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1DIR
1A1
1
47
To Seven Other Channels
48
1OE
2
1B1
2DIR
2A1
24
36
To Seven Other Channels
25
13
2OE
2B1
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
SN74ALVC164245
16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999
absolute maximum ratings over operating free-air temperature range for V
at 3.3 V (unless otherwise noted)
V
CCA
Supply voltage range: V Input voltage range, V
CCA
V
CCB
: Except I/O ports (see Note 1) –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
I/O port A (see Note 2) –0.5 V to V
I/O port B (see Note 1) –0.5 V to V Input clamp current, I Output clamp current, I
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
OK
Continuous output current, I Continuous current through each V Package thermal impedance, θ
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
at 5 V and
CCB
CCA CCB
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
+ 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This value is limited to 6 V maximum.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions for V
V V V V V I
OH
I
OL
t/v Input transition rise or fall rate 10 ns/V T
NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application
Supply voltage 4.5 5.5 V
CCB
High-level input voltage 2 V
IH
Low-level input voltage 0.8 V
IL
Input voltage 0 V
IA
Output voltage 0 V
OB
High-level output current –24 mA Low-level output current 24 mA
Operating free-air temperature –40 85 °C
A
report,
Implications of Slow or Floating CMOS Inputs
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
at 5 V (see Note 4)
CCB
, literature number SCBA004.
MIN MAX UNIT
CCB CCB
V V
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3
SN74ALVC164245
IOHHigh-level output current
mA
IOLLow-level output current
mA
I
100 µA
V
B)
V
I
mA
I
100 µA
V
B)
V
I
mA
16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999
recommended operating conditions for V
V V V V V
t/v Input transition rise or fall rate 10 ns/V T
NOTE 4: All unused inputs of the device must be held at the associated VCC or GND to ensure proper device operation. Refer to the TI application
Supply voltage 2.7 3.6 V
CCA
High-level input voltage V
IH
Low-level input voltage V
IL
Input voltage 0 V
IB
Output voltage 0 V
OA
p
p
Operating free-air temperature –40 85 °C
A
report,
Implications of Slow or Floating CMOS Inputs
electrical characteristics over recommended operating free-air temperature range for V
at 3.3 V (see Note 4)
CCA
, literature number SCBA004.
MIN MAX UNIT
= 2.7 V to 3.6 V 2 V
CCA
= 2.7 V to 3.6 V 0.8 V
CCA
V
= 2.7 V –12
CCA
V
= 3 V –24
CCA
V
= 2.7 V 12
CCA
V
= 3 V 24
CCA
CCA CCA
CCB
V V
= 5 V
(unless otherwise noted) (see Note 5)
PARAMETER TEST CONDITIONS V
= –
OH
(A to
OH
= –24
OH
=
OL
(A to
OL
= 24
OL
I
I
I
OZ
I
CC
I C C
Typical values are measured at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than at 0 or the associated VCC.
NOTE 5: V
Control inputs VI = V
A or B ports VO = V
§
CC
Control inputs VI = V
i
A or B ports VO = V
io
= 2.7 V to 3.6 V
CCA
or GND 5.5 V ±5 µA
CCB
or GND 5.5 V ±10 µA
CCB
VI = V One input at 3.4 V , Other inputs at V
or GND, IO = 0 5.5 V 40 µA
CCB
or GND 5 V 6.5 pF
CCB
or GND 5 V 6.5 pF
CCB
or GND 4.5 V to 5.5 V 750 µA
CCB
CCB
4.5 V 4.3
5.5 V 5.3
4.5 V 3.7
5.5 V 4.7
4.5 V 0.2
5.5 V 0.2
4.5 V 0.55
5.5 V 0.55
MIN TYP†MAX UNIT
4
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V
A)
I
mA
V
t
ns
CpdPower dissipation capacitance
C
50 pF
pF
SN74ALVC164245
16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range for V
CCA
= 3.3 V
(unless otherwise noted) (see Note 6)
PARAMETER TEST CONDITIONS V
IOH = –100 µA 2.7 V to 3.6 V VCC–0.2
(B to
OH
VOL (B to A)
I
Control inputs VI = V
I
I
OZ
I
CC
§
I
CC
C
Control inputs VI = V
i
C
A or B ports VO = V
io
Typical values are measured at VCC = 3.3 V, TA = 25°C.
For I/O ports, the parameter IOZ includes the input leakage current.
§
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than at 0 or the associated VCC.
NOTE 6: V
= 5 V ± 0.5 V
CCB
= –12
OH
IOH = –24 mA 3 V 2 IOL = 100 µA 2.7 V to 3.6 V 0.2 IOL = 12 mA 2.7 V 0.4 IOL = 24 mA 3 V 0.55
or GND 3.6 V ±5 µA
CCA
VO = V VI = V One input at V
or GND 3.6 V ±10 µA
CCA
or GND, IO = 0 3.6 V 40 µA
CCA
– 0.6 V, Other inputs at V
CCA
or GND 3.3 V 6.5 pF
CCA
or GND 3.3 V 8.5 pF
CCA
or GND 3 V to 3.6 V 750 µA
CCA
CCA
2.7 V 2.2 3 V 2.4
MIN TYP†MAX UNIT
V
switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figures 1 and 2)
PARAMETER
pd
t
en
t
dis
t
en
t
dis
This limit can vary among suppliers.
operating characteristics, T
PARAMETER
p
p
V
= 5 V ± 0.5 V
CCB
FROM
(INPUT)
A B 5.9 1 5.8
B A 6.7 1.2 5.8 OE OE OE OE
= 25°C
A
Outputs enabled (A or B) Outputs disabled (A or B)
TO
(OUTPUT)
B 9.3 1 8.9 ns B 9.2 2.1 9.5 ns A 10.2 2 9.1 ns A 9 2.9 8.6 ns
TEST CONDITIONS
=
L
V
= 2.7 V
CCA
MIN MAX¶MIN¶MAX
p
,f = 10 MHz
V
V
V
CCA
± 0.3 V
CCA
CCB
= 3.3 V
= 3.3 V
= 5 V
TYP
56
6
UNIT
UNIT
p
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SN74ALVC164245 16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER WITH 3-STATE OUTPUTS
SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CCA
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
F. t
G. t
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
and t
PLZ PZL PLH
and t and t
PHZ PZH
PHL
500
500
1.5 V 1.5 V
are the same as t are the same as ten. are the same as tpd.
dis
.
S1
t
PHL
6 V
GND
3 V
0 V
V
OH
V
OL
Open
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Open
6 V
GND
1.5 V1.5 V
1.5 V
1.5 V
t
PLZ
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
3 V
0 V
3 V
V
OL
V
OH
0 V
Figure 1. Load Circuit and Voltage Waveforms
6
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From Output
Under Test
(see Note A)
CL = 50 pF
16-BIT 3.3-V TO 5-V LEVEL SHIFTING TRANSCEIVER
SCAS416F – MARCH 1994 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 5 V ± 0.5 V
CCB
2 V
CCB
Open
GND
500
500
S1
SN74ALVC164245
WITH 3-STATE OUTPUTS
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 V
GND
CCB
Output
LOAD CIRCUIT
t
PHL
50% V
2.7 V
0 V
V
OH
CCB
V
OL
S1 at 2 V
Input
t
PLH
Output
OTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 , tr 2.5 ns, tf 2.5 ns. D. The outputs are measured one at a time with one transition per measurement. E. t
F. t
G. t
1.5 V 1.5 V
50% V
CCB
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
PLZ PZL PLH
and t and t and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Control
(low-level
enabling)
Output
Waveform 1
CCB
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
t
PZL
50% V
t
PZH
50% V
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
CCB
CCB
1.5 V1.5 V
20% V
80% V
t
PLZ
t
PHZ
CCB
CCB
2.7 V
0 V
V
V
OL
V
OH
0 V
CCB
Figure 2. Load Circuit and Voltage Waveforms
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7
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