Texas Instruments SN74ALVC16334DGGR, SN74ALVC16334DGVR, SN74ALVC16334DL, SN74ALVC16334DLR Datasheet
SN74ALVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Ideal for Use in PC100 Register DIMM
D
Designed to Comply With JEDEC 168-Pin
and 200-Pin SDRAM Buffered DIMM
Specification
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
description
This 16-bit universal bus driver is designed for
1.65-V to 3.6-V V
Data flow from A to Y is controlled by the
output-enable (OE
the transparent mode when the latch-enable (LE
input is low. When LE
if the clock (CLK) input is held at a high or low logic
level. If LE
is high, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLK.
When OE
is high, the outputs are in the
high-impedance state.
operation.
CC
) input. The device operates in
is high, the A data is latched
DGG, DGV, OR DL PACKAGE
)
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK
A1
A2
GND
A3
A4
V
CC
A5
A6
GND
A7
A8
A9
A10
GND
A1 1
A12
V
CC
A13
A14
GND
A15
A16
LE
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y1 1
Y12
V
CC
Y13
Y14
GND
Y15
Y16
NC
NC – No internal connection
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ALVC16334 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74ALVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999
OE LE CLK A
H X X X Z
L LXL L
LLXH H
LH↑LL
LH↑HH
LHL or H X Y
†
Output level before the indicated steady-state
input conditions were established
FUNCTION TABLE
INPUTS
OUTPUT
Y
†
0
logic symbol
‡
OE
CLK
LE
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
1
48
25
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
EN1
2C3
C3
G2
11
1
3D
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
OE
48
CLK
25
LE
SN74ALVC16334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES128C – FEBRUARY 1998 – REVISED FEBRUARY 1999
A1
47
1D
C1
CLK
To 15 Other Channels
2
Y1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
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