Texas Instruments SN74ALVC162835DGGR, SN74ALVC162835DGVR, SN74ALVC162835DL, SN74ALVC162835DLR Datasheet

SN74ALVC162835

18-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999

D

Member of the Texas Instruments

D

Widebus
EPIC

 Family

 (Enhanced-Performance Implanted

CMOS) Submicron Process

D

Ideal for Use in PC100 Register DIMM
Revision 1.1

D

Output Port Has Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)

D

Latch-Up Performance Exceeds 250 mA Per
JESD 17

D

Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages

description

This 18-bit universal bus driver is designed for

1.65-V to 3.6-V V
Data flow from A to Y is controlled by the

output-enable (OE
the transparent mode when the latch-enable (LE)
input is high. When LE is low, the A data is latched
if the clock (CLK) input is held at a high or low logic
level. If LE is low, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLK.
When OE

is high, the outputs are in the

high-impedance state.

operation.

CC

) input. The device operates in

DGG, DGV, OR DL PACKAGE

(TOP VIEW)

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28

56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29

GND
NC
A1
GND
A2
A3
V

CC

A4
A5
A6
GND
A7
A8
A9
A10
A1 1
A12
GND
A13
A14
A15
V

CC

A16
A17
GND
A18
CLK
GND

NC
NC

Y1

GND

Y2
Y3

V

CC

Y4
Y5
Y6

GND

Y7
Y8
Y9

Y10

Y1 1

Y12

GND

Y13
Y14
Y15

V

CC

Y16
Y17

GND

Y18

OE

LE

NC – No internal connection

T o ensure the high-impedance state during power up or power down, OE

should be tied to VCC through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The output port includes equivalent 26-Ω series resistors to reduce overshoot and undershoot.
The SN74ALVC162835 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC and Widebus are trademarks of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

SN74ALVC162835
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS

SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999

OE LE CLK A

H X X X Z

L HXL L
LHXH H
LL↑LL
LL↑HH
LLL or H X Y

†

Output level before the indicated steady-state
input conditions were established

FUNCTION TABLE

INPUTS

OUTPUT

Y

†

0

logic symbol

‡

27

OE

30

CLK

28

LE

3

Y1 A1

5

Y2

6

Y3

8

Y4

9

Y5

10

Y6

12

Y7

13

Y8

14

Y9

15

Y10

16

Y11

17

Y12

19

Y13

20

Y14

21

Y15

23

Y16

24

Y17

26

Y18

EN1

2C3

C3
G2

1

1

3D

54
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31

A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18

‡

This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

logic diagram (positive logic)

27

OE

30

CLK

28

LE

54

A1

1D
C1

CLK

To 17 Other Channels

SN74ALVC162835

18-BIT UNIVERSAL BUS DRIVER

WITH 3-STATE OUTPUTS

SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999

3

Y1

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 4.6 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51.

–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

I

(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

OK

±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

JA

or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

SN74ALVC162835

IOHHigh-level output current

mA

IOLLow-level output current

mA

18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS

SCES126E – FEBRUARY 1998 – REVISED FEBRUARY 1999

recommended operating conditions (see Note 4)

MIN MAX UNIT

V

V

V

V
V

∆t/∆v Input transition rise or fall rate 10 ns/V
T

NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,

Supply voltage 1.65 3.6 V

CC

VCC = 1.65 V to 1.95 V 0.65 × V

High-level input voltage

IH

Low-level input voltage

IL

Input voltage 0 V

I

Output voltage 0 V

O

p

p

Operating free-air temperature –40 85 °C

A

Implications of Slow or Floating CMOS Inputs

, literature number SCBA004.

VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8

VCC = 1.65 V –2
VCC = 2.3 V –6
VCC = 2.7 V –8
VCC = 3 V –12
VCC = 1.65 V 2
VCC = 2.3 V 6
VCC = 2.7 V 8
VCC = 3 V 12

CC

1.7

0.7

CC
CC

V

CC

V

V
V

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265