Texas Instruments SN74ALVC162834DL, SN74ALVC162834DLR, SN74ALVC162834GR, SN74ALVC162834VR Datasheet
SN74ALVC162834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Member of the Texas Instruments
Widebus
Family
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Outputs Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
description
This 18-bit universal bus driver is designed for
1.65-V to 3.6-V V
CC
operation.
Data flow from A to Y is controlled by the
output-enable (OE
) input. The device operates in
the transparent mode when the latch-enable (LE
)
input is low. The A data is latched if the clock (CLK)
input is held at a high or low logic level. If LE
is
high, the A data is stored in the latch/flip-flop on
the low-to-high transition of CLK. When OE
is
high, the outputs are in the high-impedance state.
T o ensure the high-impedance state during power
up or power down, OE
should be tied to V
CC
through a pullup resistor; the minimum value of
the resistor is determined by the current-sinking
capability of the driver.
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
The SN74ALVC162834 is characterized for operation from –40°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
1
2
3
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5
6
7
8
9
10
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12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
NC
NC
Y1
GND
Y2
Y3
V
CC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y1 1
Y12
GND
Y13
Y14
Y15
V
CC
Y16
Y17
GND
Y18
OE
LE
GND
NC
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A1 1
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
CLK
GND
DGG, DGV, OR DL PACKAGE
(TOP VIEW)
NC – No internal connection
SN74ALVC162834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUT
OE LE CLK A
Y
H X X X Z
L LXL L
LLXH H
LH↑LL
LH↑HH
LHHX Y
0
†
LHLX Y
0
‡
†
Output level before the indicated steady-state
input conditions were established, provided
that CLK is high before LE
goes high
‡
Output level before the indicated steady-state
input conditions were established
logic symbol
§
A6
47
A7
45
A8
44
A9
43
A10
42
A11
41
A12
40
A13
38
A14
37
A15
36
A16
34
A17
33
A18
31
OE
EN1
27
30
CLK
3
Y1
5
Y2
6
Y3
9
Y5
10
Y6
12
Y7
13
Y8
14
Y9
15
Y10
16
Y11
17
Y12
19
Y13
20
Y14
21
Y15
23
Y16
24
Y17
26
Y18
C3
28
G2
§
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
A1
54
A2
52
A3
51
A4
49
A5
48
2C3
8
Y4
LE
3D
1
1
SN74ALVC162834
18-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES172A – DECEMBER 1998 – REVISED FEBRUARY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
OE
CLK
Y1
1D
C1
CLK
To 17 Other Channels
LE
A1
27
30
28
54
3
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, V
O
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each V
CC
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
JA
(see Note 3): DGG package 81°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 86°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 74°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
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