Datasheet SN74ALVC162334DGGR, SN74ALVC162334DGVR, SN74ALVC162334DL, SN74ALVC162334DLR Datasheet (Texas Instruments)
SN74ALVC162334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
D
Member of the Texas Instruments
D
Widebus
EPIC
Family
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
Ideal for Use in PC100 Register DIMM
D
Output Ports Have Equivalent 26-Ω Series
Resistors, So No External Resistors Are
Required
D
Designed to Comply With JEDEC 168-Pin
and 200-Pin SDRAM Buffered DIMM
Specification
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages
description
This 16-bit universal bus driver is designed for
1.65-V to 3.6-V V
Data flow from A to Y is controlled by the
output-enable (OE
the transparent mode when the latch-enable (LE
input is low. When LE
if the clock (CLK) input is held at a high or low logic
level. If LE
is high, the A data is stored in the
latch/flip-flop on the low-to-high transition of CLK.
When OE
is high, the outputs are in the
high-impedance state.
operation.
CC
) input. The device operates in
is high, the A data is latched
DGG, DGV, OR DL PACKAGE
)
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
CLK
A1
A2
GND
A3
A4
V
CC
A5
A6
GND
A7
A8
A9
A10
GND
A1 1
A12
V
CC
A13
A14
GND
A15
A16
LE
OE
Y1
Y2
GND
Y3
Y4
V
CC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y1 1
Y12
V
CC
Y13
Y14
GND
Y15
Y16
NC
NC – No internal connection
The outputs, which are designed to sink up to 12 mA, include equivalent 26-Ω resistors to reduce overshoot
and undershoot.
T o ensure the high-impedance state during power up or power down, OE
should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ALVC162334 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
SN74ALVC162334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
OE LE CLK A
H X X X Z
L LXL L
LLXH H
LH↑LL
LH↑HH
LHL or H X Y
†
Output level before the indicated steady-state
input conditions were established
FUNCTION TABLE
INPUTS
OUTPUT
Y
†
0
logic symbol
‡
OE
CLK
LE
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
Y15
Y16
1
48
25
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
EN1
2C3
C3
G2
11
1
3D
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
1
OE
48
CLK
25
LE
SN74ALVC162334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
A1
47
1D
C1
CLK
To 15 Other Channels
2
Y1
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range, V
Input clamp current, I
Output clamp current, I
Continuous output current, I
Continuous current through each V
Package thermal impedance, θ
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 1) –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
(VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
JA
or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(see Note 3): DGG package 89°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DGV package 93°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DL package 94°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
†
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
SN74ALVC162334
IOHHigh-level output current
mA
IOLLow-level output current
mA
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
V
V
V
V
∆t/∆v Input transition rise or fall rate 10 ns/V
T
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Supply voltage 1.65 3.6 V
CC
VCC = 1.65 V to 1.95 V 0.65 × V
High-level input voltage
IH
Low-level input voltage
IL
Input voltage 0 V
I
Output voltage 0 V
O
p
p
Operating free-air temperature –40 85 °C
A
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 2
VCC = 1.65 V to 1.95 V 0.35 × V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V 0.8
VCC = 1.65 V –2
VCC = 2.3 V –6
VCC = 2.7 V –8
VCC = 3 V –12
VCC = 1.65 V 2
VCC = 2.3 V 6
VCC = 2.7 V 8
VCC = 3 V 12
CC
1.7
0.7
CC
CC
V
CC
V
V
V
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
I
mA
I
mA
C
V
V
GND
3.3 V
pF
twPulse duration
ns
D
LE↑
SN74ALVC162334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS
IOH = –100 µA 1.65 V to 3.6 V VCC–0.2
IOH = –2 mA 1.65 V 1.2
IOH = –4 mA 2.3 V 1.9
V
OH
V
OL
I
I
I
OZ
I
CC
∆I
CC
Control inputs
i
Data inputs
C
†
All typical values are at VCC = 3.3 V, TA = 25°C.
Outputs VO = VCC or GND 3.3 V 7.5 pF
o
= –6
OH
IOH = –8 mA 2.7 V 2
IOH = –12 mA 3 V 2
IOL = 100 µA 1.65 V to 3.6 V 0.2
IOL = 2 mA 1.65 V 0.45
IOL = 4 mA 2.3 V 0.4
= 6
OL
IOL = 8 mA 2.7 V 0.6
IOL = 12 mA 3 V 0.8
VI = VCC or GND 3.6 V ±5 µA
VO = VCC or GND 3.6 V ±10 µA
VI = VCC or GND, IO = 0 3.6 V 40 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3 V to 3.6 V 750 µA
=
or
I
CC
V
CC
2.3 V 1.7
3 V 2.4
2.3 V 0.55
3 V 0.55
MIN TYP†MAX UNIT
5
5.5
V
V
p
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
f
clock
t
su
t
h
‡
This information was not available at the time of publication.
Clock frequency
Setup time
Hold time
LE low
CLK high or low
Data before CLK↑
ata before
Data after CLK↑
Data after LE↑
CLK high
CLK low
CLK
high or low
VCC = 1.8 V
MIN MAX MIN MAX MIN MAX MIN MAX
‡
‡
‡
‡
‡
‡
‡
VCC = 2.5 V
± 0.2 V
‡
3.3 3.3 3.3
3.3 3.3 3.3
1.4 1.7 1.5
1.2 1.6 1.3
1.4 1.5 1.2
0.9 0.9 0.9
1.1 1.1 1.1
VCC = 2.7 V
150 150 150 MHz
VCC = 3.3 V
± 0.3 V
UNIT
ns
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
SN74ALVC162334
(INPUT)
(OUTPUT)
(INPUT)
(OUTPUT)
t
ns
PARAMETER
TEST CONDITIONS
UNIT
C
C
pF
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
f
max
t
pd
t
en
t
†
This information was not available at the time of publication.
dis
FROM
A
LE
CLK
OE Y
OE Y
TO
Y
VCC = 1.8 V
MIN TYP MIN MAX MIN MAX MIN MAX
†
switching characteristics from 0°C to 65°C, CL = 50 pF
PARAMETER
pd
FROM
A Y 1.2 3.8
CLK Y 1.1 4.8
VCC = 2.5 V
± 0.2 V
150 150 150 MHz
†
†
†
†
†
1 4.4 4.5 1.1 3.9
1 5.8 6 1.3 5
1 5.2 5.4 1 4.9
1 6.4 6.4 1.1 5.4 ns
1 4.7 5.1 1.7 5 ns
VCC = 2.7 V
TO
VCC = 3.3 V
± 0.3 V
VCC = 3.3 V
± 0.15 V
MIN MAX
UNIT
ns
UNIT
operating characteristics, T
Power dissipation
pd
capacitance
†
This information was not available at the time of publication.
= 25°C
A
Outputs enabled
Outputs disabled
= 0,f = 10 MHz
L
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
TYP TYP TYP
†
†
31 36
7 11
p
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 30 pF
(see Note A)
16-BIT UNIVERSAL BUS DRIVER
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
= 1.8 V
V
CC
2 × V
Open
GND
CC
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1 kΩ
1 kΩ
S1
SN74ALVC162334
WITH 3-STATE OUTPUTS
Open
2 × V
CC
GND
LOAD CIRCUIT
Timing
Input
t
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
VCC/2VCC/2
VCC/2VCC/2
t
PLZ
VOL + 0.15 V
t
PHZ
VOH – 0.15 V
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
SN74ALVC162334
16-BIT UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
CL = 30 pF
(see Note A)
500 Ω
500 Ω
S1
V
= 2.5 V ± 0.2 V
CC
2 × V
CC
Open
GND
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
Open
2 × V
GND
CC
LOAD CIRCUIT
Timing
Input
t
Data
Input
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Input
t
PLH
Output
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤ 2 ns, tf ≤ 2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
VCC/2 VCC/2
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
and t
PLZ
PZL
PLH
and t
and t
PHZ
PZH
PHL
VCC/2
t
su
are the same as t
are the same as ten.
are the same as tpd.
h
VCC/2VCC/2
VCC/2 VCC/2
.
dis
t
PHL
V
0 V
V
0 V
V
0 V
V
V
CC
CC
CC
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 2 × V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
CC
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VCC/2
VCC/2
t
w
VCC/2VCC/2
VCC/2VCC/2
t
VOL + 0.15 V
t
VOH – 0.15 V
PLZ
PHZ
V
0 V
V
0 V
V
V
V
0 V
CC
CC
CC
OL
OH
Figure 2. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
From Output
Under Test
CL = 50 pF
(see Note A)
Timing
Input
Data
Input
Input
Output
500 Ω
LOAD CIRCUIT
t
su
1.5 V 1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
1.5 V 1.5 V
t
PLH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
16-BIT UNIVERSAL BUS DRIVER
SCES127C – FEBRUARY 1998 – REVISED FEBRUARY 1999
PARAMETER MEASUREMENT INFORMATION
V
= 2.7 V AND 3.3 V ± 0.3 V
CC
6 V
500 Ω
1.5 V
S1
t
h
t
PHL
Open
GND
2.7 V
0 V
2.7 V
0 V
2.7 V
0 V
V
V
OH
OL
Input
Output
Control
(low-level
enabling)
Output
Waveform 1
S1 at 6 V
(see Note B)
Output
Waveform 2
S1 at GND
(see Note B)
TEST S1
t
pd
t
PLZ/tPZL
t
PHZ/tPZH
1.5 V 1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
PZL
t
PZH
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
SN74ALVC162334
WITH 3-STATE OUTPUTS
Open
6 V
GND
t
w
2.7 V
0 V
2.7 V
1.5 V1.5 V
0 V
t
PLZ
3 V
1.5 V
1.5 V
VOL + 0.3 V
t
PHZ
VOH – 0.3 V
V
V
0 V
OL
OH
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf ≤ 2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. t
F. t
G. t
PLZ
PZL
PLH
and t
and t
and t
are the same as t
PHZ
are the same as ten.
PZH
are the same as tpd.
PHL
dis
.
Figure 3. Load Circuit and Voltage Waveforms
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9
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Copyright 1999, Texas Instruments Incorporated
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